Cadence
High-Tech
SrPrincipalDesignEngineer(ChipletSolutions)
Neural analysis suggests this role is
optimal for Senior candidates.
“Sr Principal Design Engineer (Chiplet Solutions) at Cadence. Skills: Verilog RTL Design, SoC Architecture, Technical Team leadership, Chiplet Solutions. Technical leadership of complex Silicon programs. Define next generation Chiplets”
Industry & Context.
Travel: <10%
What They're Looking For.
Must Have
Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline, 12+ years’ experience in microelectronics/EDA industry, Experience of Verilog RTL Design essential, Experience of Metric Driven Verification (MDV) essential, Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential, Experience of SoC Architecture and Development essential, Experience of Technical Team leadership essential, Excellent oral and written English essential
Nice to Have
Experience of AMBA, PCIe, CXL & UCIe protocols preferred, Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred
What You'll Do.
Technical leadership of complex Silicon programs
Define next generation Chiplets
Integration of Cadence IP Solutions
Integration of partner IP Solutions
Leadership of RTL activities
Leadership of Testbench activities
Leadership of Formal Analysis activities
Leadership of Trial Synthesis activities
Quality Assurance implementation
Planning of activities and milestones
Leadership of cross-functional technical meetings
Support customer pre-sales meetings
Support customer post-sales meetings
Participate in Technical Review Meetings
Participate in Checklist Reviews
How You'll Work.
Team & Collaboration
Work closely with our Chiplet Architecture team; Leadership of cross-functional technical meetings with domain leads; Work with Global Chiplet team
Communication Scope
Excellent oral and written English; Excellent communication skills
Process & Methodology
Planning of activities and milestones
Full Job Description
## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** **Job Title: Sr Principal Design Engineer** **Location: Edinburgh, United Kingdom** **Reports to:****Design Engineering Group Director** **Job Overview:** The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) and Chiplet Solutions for a variety of High-Tech Markets. The Cadence IP & Chiplet solutions allow our Customers to tackle Silicon product development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence Vision is to deliver industry leading IP & Chiplet solutions to enable our customers to be successful across fast-moving application spaces such as Physical AI, DataCentre and High Performance Computing. The Sr Principal Design Engineer will be based in Edinburgh as part of an experienced Front-End Engineering Team, working with our Global Chiplet team in Europe, India and the USA. **Job Responsibilities:** * Technical leadership of complex Silicon programs consisting of leading-edge IP * Work closely with our Chiplet Architecture team to define next generation Chiplets * Integration of Cadence IP Solutions e.g. UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision * Integration of partner IP Solutions e.g.
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