Cadence
Sr.PrincipalDesignEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Sr. Principal Design Engineer at Cadence. Skills: VLSI, SOC verification, UVM. Lead verification strategy. Mentor and guide verification engineers”
Industry & Context.
problem solving skills
What They're Looking For.
Must Have
12+ years of VLSI industry experience in Verification, SOC level verification experience, IP or Subsystem or SOC level verification experience, develop test plans, tests, knowledge of SV, UVM, create verification environment using UVM methodology, develop bus functional models, monitors, checkers and scoreboards, experience in coverage driven verification closure, Working knowledge of verification cycle for any complex IP/SOC for atleast one/more projects, experience on complete SOC level Verification Cycle
Nice to Have
SOC level verification experience preferred
What You'll Do.
Lead verification strategy
Mentor and guide verification engineers
Create verification environment
Develop bus functional models
How You'll Work.
Team & Collaboration
collaborate and work seamlessly with design, architecture, and cross‑functional teams
Full Job Description
## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** * BTech/ MTech in Engineering * 12+ years of VLSI industry experience in Verification. * SOC level verification experience preferred * IP or Subsystem or SOC level verification experience * Should be able to develop test plans, tests * Strong knowledge of SV, UVM. Should be able to create verification environment using UVM methodology * Should be able to develop bus functional models, monitors, checkers and scoreboards. * Should have experience in coverage driven verification closure. * Strong individual contributor with good debug, problem solving skills * Working knowledge of verification cycle for any complex IP/SOC for atleast one/more projects. * Lead verification strategy and high quality execution part of SOCs/Chiplet based SOCs. * Mentor and guide verification engineers, fostering technical excellence * Strong experience on complete SOC level Verification Cycle * Ability to collaborate and work seamlessly with design, architecture, and cross‑functional teams ## **We’re doing work that matters. Help us solve what others can’t.**
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