ADCI
Hardware Development, ASIC, alexa and amazon devices
Sr.PhysicalDesignEngineer-FullChip,HardwareComputeGroup
Neural analysis suggests this role is
optimal for Senior candidates.
“Sr. Physical Design Engineer - Full Chip, Hardware Compute Group at ADCI. Skills: Physical Design, Timing Closure, SOC Design. Collaborate with architecture teams. Collaborate with timing teams”
Industry & Context.
Analytical skills
What They're Looking For.
Must Have
Bachelor’s degree or higher, 10+ years semiconductor implementation experience, Scripting experience, Proficiency in chip implementation tools, Good communication skills, Analytical skills, Ability to work closely with teams
Nice to Have
MS/PhD degree, Experience with memory compiler, Experience with formal equivalence, In depth knowledge of entire design process, Experience with DFT and DFM flows
What You'll Do.
Collaborate with architecture teams
Collaborate with timing teams
Collaborate with logic design teams
Perform bump planning
Perform hard IP integration
Perform feedthrough planning
Perform repeater insertion
Perform power grid generation
Perform interface planning
Perform interconnect planning
Perform sequential pipeline planning
Perform top-level design for testability
Drive FC methodology improvements
Coordinate collateral handoffs
Drive physical design
Perform reliability verification
How You'll Work.
Team & Collaboration
Cross-functional teams; Multiple sites
Communication Scope
Communication skills
Full Job Description
The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. Roles & Responsibilities: - Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge & Low power SOCs. - Perform I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, pin and feedthrough planning, repeater insertion, power grid generation. - Perform special interface, and interconnect planning, bus routing, sequential pipeline planning and top-level design for testability (DFT). - Be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement. - Be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR. - Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis). - Supervise and mentor other engineers Basic Qualifications: - Bachelor’s degree or higher in EE, CE, or CS - 10+ years or more of practical semiconductor implementation experience - Scripting experience with Perl, Python, tcl, shell and drive to automate flows - Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus - Must have good communication and analytical skills. - Should be able to work closely with IP Desig
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