SrLayoutEngineer-DPGLPDDR

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Job Requirements** * 4+ years of hands-on experience in physical design implementation for complex SoC or large-scale digital blocks, with demonstrated ownership from initial floor planning through tape-out. * Strong experience in block-level timing analysis and closure, including setup/hold closure across multi-mode, multi-corner (MMMC) scenarios, in collaboration with STA and signoff teams. * Shown experience working on advanced process technology nodes (e.g., 5nm, 3nm, or equivalent), with awareness of node-specific physical design challenges and constraints. * Proficiency with industry-standard place-and-route tools such as Cadence Innovus and/or Synopsys IC Compiler II, including ECO implementation and design optimization. * Hands-on expertise in physical verification and signoff closure, including DRC, LVS, antenna, and related foundry checks, with the ability to efficiently debug and resolve violations. * Strong understanding of power integrity and reliability analysis, including IR drop, electro-migration (EM), noise, coupling, and crosstalk, along with effective mitigation strategies. * Demonstrated ability to analyze and close IR/EM issues at the block level, working closely with power, signoff, and technology teams based on feedback and analysis results. * Solid foundation in digital design fundamentals, including digital electronics, microprocessors, and computer architecture, enabling effective collaboration with RTL and architecture teams. * Experience in bringing to bear automation and scripting (e.g., Tcl, Python, or equivalent) to improve physical development efficiency, quality, and turnaround time. * Exposure to AI-assisted tools and workflow