Micron Technology
Technology
SrLayoutEngineer-DPG-LPDDR
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“Sr Layout Engineer-DPG-LPDDR at Micron Technology. Skills: Analog layout, Mixed signal, High-speed serial link. Take responsibility for layout integration. Guarantee low-noise performance”
What You'll Achieve.
First-silicon success
Industry & Context.
Proactively identifying risks; Proactively resolving risks; Post-layout optimization
What They're Looking For.
Must Have
6+ years analog mixed signal experience, 6+ years high-speed serial link experience, B. E. or equivalent experience, M. Tech in VLSI Build, M. Tech in Microelectronics, M. Tech in Electronics Engineering
Nice to Have
AI/ML knowledge
What You'll Do.
Take responsibility for layout integration
Guarantee low-noise performance
Guarantee high reliability
Guarantee operation across PVT corners
Apply device physics expertise
Drive high-quality layout implementation
Complete high-speed layout techniques
Focus on impedance control
Focus on skew matching
Focus on crosstalk mitigation
Work closely with designers
Work closely with architects
Enable layout-aware build
Proactively identify risks
Proactively resolve risks
Lead post-layout optimization
Lead sign-off activities
Provide technical mentorship
Conduct design reviews
Contribute to guidelines
Contribute to quality improvement
Support data-driven optimization
Support layout automation initiatives
Support improved debug workflows
Support improved correlation workflows
How You'll Work.
Team & Collaboration
Work closely with designers; Work closely with architects
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join our ambitious team in Hyderabad as a Senior Analog Layout Engineer-DPG-LPDDR and contribute to our mission of transforming information into intelligence. You will be responsible for the layout and integration of key analog blocks, ensuring outstanding performance and reliability across advanced process technologies. * Take responsibility for the layout and integration of essential analog blocks, guaranteeing low-noise performance, high reliability, and strong operation across PVT corners for advanced process technologies. * Must have 6+years of proven hands-on experience on analog mixed signal and high-speed serial link modules * Apply strong device physics expertise to drive high-quality layout implementation, including transistor matching strategies, well and substrate engineering, parasitic optimization, and EM/ESD reliability considerations. * Complete and review high-speed layout techniques for sensitive analog and mixed-signal paths, focusing on impedance control, skew matching, shielding, isolation, and crosstalk mitigation. * Work closely with circuit designers and architects to enable layout-aware build, proactively identifying and resolving parasitic, noise, and performance risks early in the design cycle. * Lead post-layout optimization and sign-off activities, including DRC/LVS, EM/IR analysis, and correlation of post-layout simulations with silicon or lab data. * Provide technical mentorship and conduct design reviews for complex blocks, contributing to guidelines, quality improvement, and first-silicon success. * Leverage AI/ML knowledge as a benefit to support data-driven optimization, layout automation initiatives, and improved debug and corr
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