Renesas Electronics
Technology
Sr.LayoutEngineer
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“Sr. Layout Engineer at Renesas Electronics. Skills: Mask layout design, Power semiconductor device. Play key role in mask layout design. Play key role in development of next-generation LV”
What You'll Achieve.
Accelerate product industrialization
Industry & Context.
Optimize performance
What They're Looking For.
Must Have
More than 5 years of experience in mask layout design for power semiconductor device, More than 10 years of experience in mask layout design for power semiconductor device, Intermediate-level proficiency in both written and spoken English and Japanese, English - Can engage in daily conversation (around TOEIC 600 points), Japanese - Can engage in business conversation (above JLPT 2)
What You'll Do.
Play key role in mask layout design
Play key role in development of next-generation LV
Accelerate product industrialization
Perform chip layout design for LV/MV shield-gate trench
Perform verification of mask design rule check
Define mask specification
Perform scribe design
Perform accessory layout
Build related documents
How You'll Work.
Team & Collaboration
Close collaboration with process integration team; Collaboration with external foundry partners; Communication with product development engineer; Communication with process technology engineer
Communication Scope
Written English; Spoken English; Written Japanese; Spoken Japanese
Process & Methodology
Schedule adjustment
Full Job Description
We are looking for a new engineer for mask layout design. The successful candidate will play a key role in the mask layout design and development of next-generation LV and MV shielded-gate trench MOSFET technologies. This role involves close collaboration with process integration team and external foundry partners to drive innovation, optimize performance, and accelerate product industrialization. Mask layout design • Chip layout design for LV/MV shield-gate trench MOSFET based on the design manual/rule (Virtuoso etc.) • Verification of mask design rule check (Calibre etc.) T/O procedures • Schedule adjustment, Provenance tracking • Define mask specification (Pellicle specification, inspection specification etc.) • Scribe design, accessary layout such as alignment mark, inspection mark • Build the related documents including shot map ## Qualifications • More than 5 years of experience in mask layout design for power semiconductor device • Communication skills with product development engineer, process technology engineer. • Intermediate-level proficiency in both written and spoken English and Japanese • More than 10 years of experience in mask layout design for power semiconductor device • English - Can engage in daily conversation (around TOEIC 600 points) • Japanese - Can engage in business conversation (above JLPT 2) ## Additional Information ルネサスは、「To Make Our Lives Easier 」(人々の暮らしを楽“ラク”にする)というPurposeの下、組み込み半導体ソリューションを提供します。高品質とシステムレベルノウハウを兼ね備えた組み込み半導体のリーダーとして、自動車、産業、インフラ・IoT分野向けに、ハイパフォーマンスコンピューティング、組み込みプロセッシング、アナログ&コネクティビティ、そしてパワーを含めた幅広い製品ポートフォリオを軸とした、スケーラブルで包括的なソリューションを提供しています。 ルネサスは、30か国以上で22,000 人を超える多様性あふれる従業員と共に、限界に挑戦しながら、デジタライゼーションを通じてユーザエクスペリエンスを充実化させ、新たなイノベーションの時代を切り開いていきます。そして世界中の人々やコミュニティの未来のために、持続可能で省エネ効果の高いソリューションの開発に全力で取り組み、「To Make Our Lives Easier 」を実現します。 ルネサスで実現できること * キャリアをスタート、そしてキャリアアップ: 4つのプロダクトグループをはじめ、さまざまな部門において技術職として、また幅広いビジネスの経験を積むことができます。ハードウェア、ソフトウェアの専門知識を深めたり、新しいことにチャレンジしたりする機会があります。 * やりがいとインパクトのある仕事をする: 革新的な製品とソリューションの開発に関わることにより、
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