Tenstorrent
AI
Sr.Engineer,RTLImplementation
Neural analysis suggests this role is
optimal for Senior candidates.
“Sr. Engineer, RTL Implementation at Tenstorrent. Skills: RTL Implementation, CPU Design, Physical Design. Perform synthesis. Optimize core configurations”
What You'll Achieve.
Deliver a functional, timing, and power-converged design; Optimize CPU designs for best PPA; Improve development efficiency
Industry & Context.
Eligibility to access U. S. export-controlled technology, Compliance with U. S. export laws (EAR)
What They're Looking For.
Must Have
Proficient in RTL coding (Verilog/VHDL), Familiar with industry-standard tools for simulation and power analysis, Skilled in synthesis, place and route tools including flows and physical design methodology, Background in CPU micro-architecture
Nice to Have
Experienced in high-performance physical design
What You'll Do.
Optimize core configurations
Drive physical design experiments
Evaluate physical design results
Enhance physical design environment
Improve development efficiency
How You'll Work.
Team & Collaboration
Collaborate closely with core micro-architects; Collaborating with DV, PD, RTL and performance teams; Work in a deeply technical, highly collaborative team
Full Job Description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to iterate through front-end CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Perform synthesis and initial place and route for new and legacy designs. Collaborate closely with core micro-architects to optimize core configurations for best PPA. Use innovative techniques to optimize power, performance, and area while driving physical design experiments and evaluating results. Enhance physical design environment, tools, an
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