Tenstorrent
AI technology
Sr.Engineer,DesignVerification,SystemIP
Neural analysis suggests this role is
optimal for Senior candidates.
“Sr. Engineer, Design Verification, System IP at Tenstorrent. Skills: SystemVerilog, UVM, Design Verification, Coverage closure. End-to-end verification. Ensure functional correctness”
What You'll Achieve.
Final coverage closure
Industry & Context.
Debugging complex design issues; Debugging verification issues
Eligibility to access U. S. export-controlled technology, Compliance with U. S. export laws
What They're Looking For.
Must Have
SystemVerilog, UVM, AXI, ACE, CHI, PCIe, Python, Perl, TCL, Bash
Nice to Have
AI/ML systems, Automation tools, AI-assisted tools
What You'll Do.
End-to-end verification
Ensure functional correctness
Ownership of verification process
Specification understanding
How You'll Work.
Team & Collaboration
Working closely with cross-functional teams; Collaborating across architecture; Collaborating across RTL; Collaborating across validation teams
Full Job Description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure. This role is hybrid , based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM. You enjoy debugging complex design and verification issues and working closely with cross-functional teams. You’re comfortable building verification environments from scratch and driving coverage closure. You have familiarity with standard bus protocols and modern verification tools. What We Need Experience owning block or subsystem-level verification from test planning to sign-off. Strong understanding of constrained-random verification, coverage analysis, and regression debugging. Familiarity with protocols such as
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