Nxp
SrDFTEngineer
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“Sr DFT Engineer at Nxp. Skills: DFT methodologies, ATPG tools, low-power DFT. Design DFT architectures. Implement DFT architectures”
What You'll Achieve.
robust testability; high-quality silicon
Industry & Context.
problem-solving
What They're Looking For.
Must Have
DFT methodologies: Scan, MBIST, LBIST, JTAG, industry standard ATPG tools, UPF/CPF-based low-power DFT, fault models (stuck-at, transition, path delay), physical design constraints for DFT, silicon debug and ATE bring-up
Nice to Have
SoC level DFT, high-speed interfaces and DFT for mixed-signal blocks
What You'll Do.
Design DFT architectures
Implement DFT architectures
Verify DFT architectures
Define DFT architecture
Implement scan insertion
Integrate scan insertion
Develop ATPG patterns
Integrate ATPG patterns
Implement memory BIST
Perform DFT verification
Optimize test coverage
Optimize pattern count
How You'll Work.
Team & Collaboration
work closely with RTL; work closely with physical design; work closely with verification teams; Collaborate with RTL teams; Collaborate with physical design teams; Work with ATE teams
Communication Scope
communication skills
Full Job Description
Senior DFT Engineer: You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs. You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon. Key Responsibilities -Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan). -Develop and integrate scan insertion, test compression, and ATPG patterns. -Implement memory BIST and logic BIST strategies. -Collaborate with RTL and physical design teams for DFT insertion and timing closure. -Perform DFT verification at RTL and gate-level simulations. -Work with ATE teams for test program development and silicon bring-up. -Optimize test coverage, pattern count, and test time. Required Skills -Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG. -Hands-on experience with industry standard ATPG tools. -Proficiency in UPF/CPF-based low-power DFT. -Knowledge of fault models (stuck-at, transition, path delay). -Familiarity with physical design constraints for DFT. -Experience in silicon debug and ATE bring-up. Preferred Qualifications \- Pas experience with SoC level DFT -Exposure to high-speed interfaces and DFT for mixed-signal blocks. -Strong problem-solving and communication skills. Education -Bachelor’s or Master’s in Electrical/Electronics Engineering. [More information about NXP in India...](https://www.nxp.com/company/about-nxp/worldwide-locations/india:INDIA) #LI-9415
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