NVIDIA
AI hardware
SoftwareR&DEngineer,VLSIPhysicalDesignNewCollegeGrad2026
“Software R&D Engineer, VLSI Physical Design - New College Grad 2026 at NVIDIA. Skills: VLSI Physical Design Algorithms, C++, optimization engines, machine learning. Invent new optimization engines that fuse traditionally independent engines (e. g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.. Improve algorithms (in C++) for gate-level sizing, buffering, useful clock s”
What You'll Achieve.
increasing chip frequency; minimizing power consumption; improving PPA
Industry & Context.
optimization engines; improve algorithms; problem-solving
What They're Looking For.
Must Have
Masters or PhD in Electrical Engineer or Computer Science (or equivalent experience), Experience with VLSI algorithms development using C++, Understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc., Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python.
Nice to Have
C++14 or newer experience, such as lambdas and concurrency., Understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA., Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc., Highly driven to craft software towards improving PPA with a dedication to continuous improvement., Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design.
What You'll Do.
Invent new optimization engines that fuse traditionally independent engines (e. g.
co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
Improve algorithms (in C++) for gate-level sizing
and incremental parasitic extraction.
Own the whole process from discovery and invention of new optimization opportunities
to developing solutions and working directly inside design teams to facilitate deployment.
How You'll Work.
Team & Collaboration
working directly inside design teams to facilitate deployment.
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