NVIDIA

AI hardware

SoftwareR&DEngineer,DigitalLogicSynthesisNewCollegeGrad2026

$116–219k Santa Clara, California, United States FULL TIME Remote Friendly
The Brief

“Software R&D Engineer, Digital Logic Synthesis - New College Grad 2026 at NVIDIA. Skills: RTL synthesis, digital logic optimization, EDA software, C++, machine learning. Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation. Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA”

What You'll Achieve.

improve PPA; see your successes directly realized in the world's best AI hardware

Industry & Context.

AI hardware
Problems you'll solve

optimization; analysis; problem-solving

What They're Looking For.

Must Have

MS or PhD in Electrical Engineering or Computer Science (or equivalent experience), Experience with EDA software and/or VLSI flows with focus in logic synthesis or digital optimization, CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing), Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent), Experience in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers

Nice to Have

Previous experience involving RTL logic synthesis and multi stage logic optimization is a plus, Experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization, Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc., Experience with various machine learning techniques

What You'll Do.

Invent and develop new algorithms for RTL synthesis

digital logic optimization

graph-based RTL traversal

Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA

Develop strategies for rapidly analyzing the RTL change impact on timing

and power delivery on design

Prototype and evaluate ML methods (e. g.

models) to guide optimization integrate successful approaches into production

Explore high performance algorithms for clustering

min cost tree covering (technology mapping)

datapath implementation and other details of logic synthesis

especially that efficiently incorporate human insight

Own the whole process from discovery and invention of new optimization opportunities

to developing solutions and working directly inside design teams to facilitate deployment

How You'll Work.

Team & Collaboration

working directly inside design teams to facilitate deployment

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