Micron Technology
Semiconductor
SOCTimingAnalysis(STA)Engineer,HBM
Neural analysis suggests this role is
optimal for Senior candidates.
“SOC Timing Analysis (STA) Engineer, HBM at Micron Technology. Skills: Static timing analysis, Timing sign-off, Constraint development, Timing closure. Own chip-level static timing analysis. Own chip-level sign-off”
Industry & Context.
Debug skills; Root cause analysis
What They're Looking For.
Must Have
10+ years industry experience, Full timing sign-off ownership, Multiple tape-outs, 5 nanometers or below, Synopsys PrimeTime expertise, Cadence Tempus expertise, Advanced timing concepts expertise, Multi-mode multi-corner analysis, On-chip variation techniques, Signal integrity analysis, Crosstalk analysis, Power-aware timing, Develop complex SDC constraints, Full RTL-to-GDS flow experience, Synthesis experience, Placement experience, Clock tree synthesis experience, Routing experience, Physical sign-off experience, Hierarchical static timing analysis, Timing-driven collaboration
Nice to Have
DFT concepts exposure, Scan exposure, MBIST exposure, Built-in redundancy analysis exposure, Built-in repair exposure, Debug exposure, Bachelor's degree, Master's degree, Familiarity with foundry PDKs, Familiarity with Liberty timing models, Familiarity with ECSM noise models, Familiarity with CCS noise models, Familiarity with advanced process variation modeling, Excellent analytical skills, Excellent debug skills, Excellent communication skills, Present timing status clearly, Present timing risks clearly, Present sign-off readiness clearly
What You'll Do.
Own chip-level static timing analysis
Own chip-level sign-off
Cover all timing checks
Develop SDC for clock domains
Develop SDC for reset trees
Develop SDC for HBM interfaces
Develop SDC for MBIST
Develop SDC for configuration logic
Ensure sign-off quality
Ensure reuse across generations
Drive timing closure at block level
Drive timing closure at subsystem level
Drive timing closure at full-chip level
Perform critical path analysis
Perform timing engineering change orders
Collaborate with physical design teams
Perform MMMC timing analysis
Perform setup closure
Perform CDC timing analysis
Lead signal integrity analysis
Lead crosstalk analysis
Identify noise-induced timing violations
Implement mitigation strategies
Conduct DFT timing analysis
Conduct scan chain timing analysis
Conduct ATPG mode constraints
Conduct MBIST timing closure
Conduct JTAG interface timing
Provide early STA feedback
Develop automation scripts
Develop automation flows
Extract timing reports
Report sign-off readiness
Perform post-silicon timing correlation
Analyze silicon measurement data
Identify systematic discrepancies
Feed learnings into timing models
Feed learnings into tool settings
Feed learnings into methodology updates
Engage with EDA tool vendors
Evaluate new features
Drive methodology enhancements
Define STA methodology
Drive STA methodology
Define sign-off standards
Drive sign-off standards
Define timing closure best practices
Drive timing closure best practices
Lead readiness reviews
Lead tape-out sign-off
Mentor junior engineers
Grow junior engineers
Contribute to design documentation
Contribute to timing sign-off reports
Contribute to constraint specifications
Contribute to block-level timing
Collaborate with Physical Design
Collaborate with RTL Design
Collaborate with Verification
Collaborate with Product Engineering
Collaborate with Test teams
Ensure timing requirements are met
How You'll Work.
Team & Collaboration
RTL design teams; Physical design teams; Architecture teams; DFT teams; Verification teams; Product teams; Cross-functional teams
Communication Scope
Present timing status; Present timing risks; Present sign-off readiness
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. You will be part of the Heterogeneous Integration Group (HIG), owning chip-level static timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, design for test (DFT), verification, and product teams to ensure timing integrity from initial design through tape-out. This is a hands-on senior technical role focused on chip-level static timing analysis ownership, timing closure, methodology development, and pre- and post-silicon timing correlation. Job Description ### Responsibilities will include, but are not limited to: * Own end-to-end chip-level static timing analysis and sign-off, covering all timing checks including setup, hold, recovery, removal, and data-to-data across all process corners, operating modes, and voltage and temperature conditions. * Develop, maintain, and validate comprehensive Synopsys Design Constraints (SDC) for all clock domains, reset trees, high-bandwidth memory (HBM) physical interfaces, Joint Test Action Group (JTAG), memory built-in self-test (MBIST), design for test (DFT), and configuration logic, ensuring sign-off quality and reuse across design generations. * Drive timing closure at block, subsystem, and full-chip levels through critical path analysis, timing engineering change orders (ECOs), and close collaboration with physical design teams on placement, clock tree synthesis (CTS), and routing to meet timing targets. * Perform multi-mode, multi-corner (MMMC) timing analysis including setup and hold closure, clock domain crossing (CDC) timing, and application of on-chip variation derates (OCV, AOCV, POCV) appropriate for advanced technology nodes. * Lead signal integrity and cro
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