SoCPlatformSoftwareEngineeringManager,AnnapurnaLabsMachineLearningAcceleration,AWS

One C++ codebase. Three radically different execution environments. We're looking for an engineering manager who thinks in terms of platforms, abstractions, and portable software architecture — and can lead a team that ships all three. Our SoC HAL (Hardware Abstraction Layer) team builds the platform software layer for AWS's custom Trainium and Inferentia ML accelerator chips. The HAL is a shared library that boots, configures, and manages every hardware block on the SoC — 270+ instances per chip — and the same source tree compiles and runs on SystemVerilog DPI for chip verification, QEMU for system emulation, and Carbon OS in microcontrollers within the AWS production fleet. Your platform abstractions are what make this possible, and your APIs are the interface that 100's of engineers across verification, emulation, and production use to interact with the chip. Tech stack: C++17, CMake, GoogleTest, Python, SystemVerilog DPI, SPI, APB/AXI bus protocols, PCIe, UCIe, HBM, PLL, custom IPs As the SoC Platform Software Manager, you will: - Manage, coach, and grow a team of 6 engineers — set technical direction, own hiring, and create an environment where strong engineers want to stay - Own the platform abstraction layer that enables one C++ codebase to compile and run correctly across three target environments with fundamentally different runtime characteristics - Shape the external API contracts that verification, emulation, and production teams build on — balancing stability for consumers against the need to evolve as new chip generations arrive - Drive the architecture of our C++ template metaprogramming framework that generates type-safe register interfaces for every hardware block, and our BUTR (Built-in Unit Test for Registers) and HITL (Hardware-in-the-Loop) test infrastructure - Build and maintain the CI/CD and validation strategy that catches integration issues across all three platforms before they reach customers - Coordinate across chip architects, RTL design