Micron Technology
Semiconductor
SMTSPhysicalDesignEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“SMTS Physical Design Engineer at Micron Technology. Skills: Physical Design, Tape-out, Timing Closure, Power Integrity. Define and implement full chip floorplans. Coordinate custom analog block placement”
What You'll Achieve.
Carry high-speed interface innovations from architecture to tape-out; Foundational hire for growing program; Execution early leads to follow-on projects
Industry & Context.
Creative problem-solving; Debugging; Root-cause analysis; Troubleshooting
What They're Looking For.
Must Have
BS, MS, or PhD in Electrical Engineering, 8–15 years of physical design experience, at least one complete front-to-back tape-out, Hands-on proficiency with Cadence Innovus, Hands-on proficiency with Cadence Tempus, Hands-on proficiency with Mentor Calibre, Experience integrating hard macros, Ability to communicate clearly with non-PD engineers
Nice to Have
Experience with mixed-signal or analog-adjacent chip physical design, Familiarity with high-speed I/O pad ring design, Experience with power domain implementation using UPF/CPF, Proficiency with Cadence Voltus or Apache Redhawk, Familiarity with Synopsys IC Compiler 2, Experience with signoff ECO flows, Prior experience carrying primary PD responsibility
What You'll Do.
Define and implement full chip floorplans
Coordinate custom analog block placement
Manage analog/digital partitioning
Define I/O ring architecture
Allocate block-level area
Design and implement chip power distribution network
Coordinate analog supply isolation
Coordinate guard ring placement
Address substrate noise considerations
Execute full-chip place-and-route
Optimize routed and optimized database
Perform static timing analysis
Identify and resolve timing violations
Coordinate constraint refinement
Perform IR drop and electromigration analysis
Identify and resolve PDN weaknesses
Execute and close DRC
Manage waiver process for violations
Implement scan chain insertion
Work on ATPG pattern generation
Work on test coverage targets
Interface with foundry on PDK questions
Manage tape-out submission requirements
Maintain PD methodology documentation
Maintain floorplan rationale records
How You'll Work.
Team & Collaboration
Work closely with Chip Lead; Work with analog team; Work with verification team; Engage broader team; Working across disciplines
Communication Scope
Communicate clearly
Process & Methodology
Drive implementation decisions, Manage priorities
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As the Physical Design Engineer, you will own the complete back-end implementation of a high-speed interface chip program — from synthesis netlist through GDSII tape-out. This is a full-flow PD role on a small, senior team spanning analog design, layout, silicon characterization, digital design, and verification — united around the goal of carrying high-speed interface innovations from architecture to tape-out. You will be the primary PD voice, working closely with the Chip Lead on timing and constraints, with the analog team on mixed-signal floorplanning considerations, and with the verification team on DFT and scan implementation. The program includes contractor support that will grow as the program scales, but the expectation is that you can drive implementation decisions independently, leverage available resources effectively, and know when to engage the broader team. The ideal candidate brings not just technical depth but creative problem-solving ability — the capacity to find non-obvious paths to closure when standard approaches don't apply cleanly to a mixed-signal PHY environment. This is a foundational hire for a growing program, and strong execution early is expected to lead to follow-on projects of increasing scope, team size, and PD complexity. **Responsibilities** * **Floorplanning:** Define and implement full chip floorplans in close collaboration with the analog design team — including custom analog block placement, analog/digital partit
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