SMTSDesignVerificationEngineer

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As the Design Verification Engineer, you will own pre-silicon functional verification for a high-speed interface chip program. Working on a small, senior team spanning analog design, layout, silicon characterization, and digital design, you will build and execute the verification environment that gives the team confidence in the RTL before silicon is committed. This is a full-ownership DV role. You will write the DV plan, build the testbench infrastructure, develop directed and constrained-random tests, close coverage, and support the transition from simulation to post-silicon bring-up. The program integrates a fully custom analog PHY alongside soft IP functions including Error Counting, Eye Monitor control, and I2C management interface — providing a technically interesting and varied verification scope well beyond standard digital block verification. A distinctive aspect of this role is the opportunity — and expectation — to stay engaged through post-silicon bring-up. Your simulation environments, coverage models, and debug waveforms will be directly leveraged in the lab during chip characterization. This is a foundational hire for a growing program, and strong execution early is expected to lead to follow-on projects of increasing scope, team size, and verification complexity. **Responsibilities** * **DV Planning:** Develop and maintain the full-chip DV plan covering all soft IP blocks and top-level integration; define coverage targets, test prioriti