SMTSAnalogDesignEngineer,Mixed-SignalPHY(Clocking&High-SpeedI/O)

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As a Principal Analog Design Engineer, you will be a core technical contributor on a small, senior team spanning analog design, layout, silicon characterization, digital design, and physical design — united around the goal of preparing high-speed interface innovations for high-confidence product adoption. The analog design scope is broad and deep, with clocking as a primary technical focus, but the program values engineers who bring perspective across the full signal chain. Key design domains include clocking architecture (PLL/DLL, clock distribution, jitter budgeting, clock recovery), transmitter design (high-speed output drivers, pre-emphasis, swing/impedance control), receiver design (sense amplifiers, CTLE/DFE equalization, samplers), bias and reference generation, and calibration architecture. The circuits are custom and original — this is not integration or maintenance work. The goal is to push the boundaries of what is possible in high-speed signaling and validate those boundaries with real hardware data. This is a long-term opportunity on an active program with real momentum — strong execution early is expected to lead to follow-on projects of increasing scope and complexity. **Responsibilities** * **Circuit Design:** Own the design of one or more custom analog blocks from specification through schematic, simulation, and layout review — with clocking (PLL, DLL, CDR) as the primary focus and transmitter/receiver circuits as valued secondary expe