Normal Computing
semiconductor
SiliconArchitect,DiffusionASICs
Neural analysis suggests this role is
optimal for Senior candidates.
“Silicon Architect, Diffusion ASICs at Normal Computing. Skills: AI accelerator architecture, Microarchitecture design, Hardware specification, FPGA prototyping. Define architecture and microarchitecture of novel AI accelerator compute blocks. Translate workload analysis and research findings into hardware specifications”
What You'll Achieve.
Contributions will be visible in the chip when it tapes out; Chip will be the silicon behind a generation of image and video AI
Industry & Context.
Make the call when the data is incomplete; Defend PPA tradeoffs at every level; Reason across the full stack; Run toward the hard stuff; Steady in ambiguity; Comfortable when data is incomplete; Take the hardest problem on the board first
What They're Looking For.
Must Have
Substantial experience in architecture or microarchitecture of high-performance digital systems, AI accelerators, compute engines, or similarly complex logic, Fluency moving between algorithm-level analysis and hardware specification, Experience with simulation-driven architecture, Familiarity with quantization and reduced-precision approaches for inference, Experience writing microarchitecture specifications, Working closely with RTL engineers through implementation, Proficiency in Python or C++ for performance modeling and analysis, Familiarity with SystemVerilog or equivalent RTL, Comfort operating in an environment where the architecture is actively being discovered
Nice to Have
PhD welcome
What You'll Do.
Define architecture and microarchitecture of novel AI accelerator compute blocks
Translate workload analysis and research findings into hardware specifications
Reason across the full stack and defend PPA tradeoffs
Partner with compiler lead on ISA co-design
Own FPGA prototyping work
Stay current with AI accelerator research landscape
How You'll Work.
Team & Collaboration
Work directly alongside lead architect and research engineers; Work closely with RTL engineers through implementation; Partner with compiler lead on ISA co-design; Articulate why under scrutiny from lead architect and research team
Communication Scope
Articulate clearly where Normal's approach differs
Full Job Description
NORMAL COMPUTING | INCREDIBLE OPPORTUNITIES The Normal Team builds foundational software and hardware that help move technology forward, supporting the semiconductor industry, critical AI infrastructure, and the broader systems that power our world. We work as one team across New York, San Francisco, Copenhagen, Seoul, and London. YOUR ROLE IN OUR MISSION Look at the AI accelerator roadmaps coming out of every major silicon company right now and you will notice something strange: they are all building the same chip. Bigger systolic arrays. More HBM. More of the same architecture, scaled harder. The industry has placed a collective bet that the way to win the next decade of AI inference is to refine the GPU paradigm until it cannot be refined any further. We know that bet is wrong. Normal is building ASICs purpose-built for image and video diffusion inference, grounded in the physics of computation rather than the assumptions everyone else has inherited. The compute substrate has to be invented, not specified, and we are looking for the person who wants to help invent it. You will work directly alongside our lead architect and research engineers, contributing across the full architecture stack: compute core microarchitecture, memory subsystem, interconnect, and the FPGA prototyping that proves the decisions before silicon. The team is small. The scope is wide. The architecture is being shaped now, not refined, and your contributions will be visible in the chip when it tapes out. If the appeal of working on a chip that has to be invented is greater to you than iterating on one that already exists, keep reading. RESPONSIBILITIES - Help define the architecture and microarchitecture of novel AI accelerator compute blocks. PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one
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