NVIDIA
AI, Accelerated Computing, Computer Graphics, PC Gaming
SeniorVLSICADEngineer
“Senior VLSI CAD Engineer at NVIDIA. Skills: VLSI CAD flow development, EDA tool development and deployment, Scripting languages (Bash, TCL, Python, Perl, Makefile). Build flows and methodology around vendor EDA tools to streamline circuit design and verification workflows. Bring up compiler workspaces for new projects”
What You'll Achieve.
Streamline circuit design and verification workflows; Enable circuit designers to iterate with agility; Ensure internal and external customer teams are ready for each release; Support sound design decisions; Streamline design reviews
Industry & Context.
Solving hard scalability challenges; Triage and resolve bugs related to RAM compiler builds
What They're Looking For.
Must Have
Minimum of 5+ years of CAD flow developments and design methodology in VLSI, Good programming skills in multiple languages (Bash, TCL, Python, Perl, Makefile), Prior experience with development, testing and deployment of EDA tools, Self-starter with passion for growth, real enthusiasm for continuous learning and sharing findings across the team
Nice to Have
Experience working with industry standard EDA tools like HSPICE, PrimeSim-XA, ESP, NanoTime/PrimeTime, Totem/SeaHawk, Knowledge of DC/Transient, Cross corner PVT and Monte Carlo simulations, Previous work in VLSI, ASIC, or EDA is a definite plus, Ability to use the latest AI tools to improve design productivity, Experience in evaluating CAD products and driving EDA vendors to meet the team’s requirements
What You'll Do.
Build flows and methodology around vendor EDA tools to streamline circuit design and verification workflows
Bring up compiler workspaces for new projects
Ensure internal flows
and tools are in sync across a multi-project development environment
Develop and maintain regression suites to validate design quality
Optimize regression infrastructure
Own and manage the release process for custom RAM circuit macros
Gatekeeping all collateral
Coordinating with management on release schedules
Ensuring internal and external customer teams are ready for each release
Ensure seamless integration of RAM compilers into PNR flows
Understand how compilers are used downstream
Triage and resolve bugs related to RAM compiler builds
Maintain versioned records of tool and infrastructure for each design release
Own the web front-end that circuit designers use to access simulation data and interact with design collateral
Ensure data is presented clearly to support sound design decisions and streamline design reviews
How You'll Work.
Team & Collaboration
Collaborate with world-class circuit design, layout, and technology teams across geographies; Engage directly with leading EDA vendors; Collaborate with circuit design, layout, technology, and 3rd party EDA vendor teams distributed across geographies and time zones
Process & Methodology
Own and manage the release process for custom RAM circuit macros, Coordinating with management on release schedules
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