AST SpaceMobile
cellular broadband network in space
SeniorVerificationEngineer
“Senior Verification Engineer at AST SpaceMobile. Skills: SystemVerilog, UVM, FPGA verification, testbench architecture, functional coverage, simulation-based verification. design, develop, and execute comprehensive verification strategies for complex FPGA designs. Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs”
What You'll Achieve.
ensure quality and completeness; coverage closure; release signoff
Industry & Context.
analytical and debugging skills
Ability to work in a standard office environment, Ability to use a computer for extended periods, Occasional lab work for FPGA bring-up and debug
What They're Looking For.
Must Have
4–8 years of hands-on experience in functional verification, Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
Nice to Have
Familiarity with cadence tools like Xcelium, Familiarity with Xilinx Vivado, Experience with hardware/software co-verification, Knowledge of high-speed interfaces (AXI, AXI‑Stream, DDR, SPI)
What You'll Do.
and execute comprehensive verification strategies for complex FPGA designs
Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs
Create and execute verification plans
directed and constrained-random test scenarios
and functional coverage
Perform simulation-based verification of FPGA designs using industry-standard simulators
Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers
Integrate and maintain VIPs
Support FPGA bring-up
and debug activities on FPGA platforms and evaluation boards
and test plans to ensure quality and completeness
Support regression runs
How You'll Work.
Team & Collaboration
cross-functional collaboration with design and system teams; Ability to work effectively in cross-functional teams
Communication Scope
Excellent written and verbal communication skills
Process & Methodology
own verification tasks end-to-end
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