Renesas Electronics
Tech / AI / Software
SeniorStaff,RTLDesignEngineer
Neural analysis suggests this role is
optimal for mid candidates.
“Senior Staff, RTL Design Engineer at Renesas Electronics. Skills: RTL Design, Verilog/SystemVerilog, Chiplet based power efficient chips, Timing Closure, Physically Aware Design Flows, Low-power design techniques, Multi-clock domain architectures, Protocol knowledge (UCIe, AHB/AXI/CHI), Memory controller design. Design and implement RTL for IPs and chip level using Verilog/SystemVerilog and industry-standard methodologies. Optimize RTL for timing, power, and area targets while ensuring design sc”
What You'll Achieve.
deliver world-class semiconductor solutions; ensuring design scalability; ensure functional correctness and coverage goals; achieve coverage goals
Industry & Context.
problem solving
What They're Looking For.
Must Have
BTech/MTech in Electrical/Electronic Engineering, Computer Engineering or Computer Science with hardware engineering experience of 8+ years in IP/chip-level RTL design, Experience in D2D protocols like UCIe or Bunch-of-wires, Proven track record in timing closure and physically aware design flows, understanding of synthesis, STA, and power optimization techniques, Experience with low-power design techniques and multi-clock domain architectures, Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers
Nice to Have
Domain knowledge of clocking, system modes, power management, debug, security is a plus
What You'll Do.
Design and implement RTL for IPs and chip level using Verilog/SystemVerilog and industry-standard methodologies
Optimize RTL for timing
and area targets while ensuring design scalability
Contribute to methodology improvements for design implementation and timing closure
Provide technical leadership and guidance to junior engineers
Provide support to functional validation teams in post silicon debug
How You'll Work.
Team & Collaboration
collaborating across architecture, verification, and physical design teams; Work closely with architecture, firmware, and physical design teams during development and implementation; Collaborate with verification teams to ensure functional correctness and coverage goals; Work closely with synthesis and physical design teams for PPA analysis and convergence; Work with DFT teams to achieve coverage goals
Communication Scope
communication skills (written and verbal)
Full Job Description
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. We are seeking a highly experienced Senior Staff RTL Design Engineer to join our SoC development team. This role involves RTL design for chiplet based power efficient chips and collaborating across architecture, verification, and physical design teams to deliver world-class semiconductor solutions. Job Summary * Design and implement RTL for IPs and chip level using Verilog/SystemVerilog and industry-standard methodologies * Optimize RTL for timing, power, and area targets while ensuring design scalability * Work closely with architecture, firmware, and physical design teams during development and implementation * Collaborate with verification teams to ensure functional correctness and coverage goals * Work closely with synthesis and physical design teams for PPA analysis and convergence * Wo
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