Renesas Electronics
Tech / AI / Software
SeniorStaffEngineer,DigitalDesign
Neural analysis suggests this role is
optimal for mid candidates.
“Senior Staff Engineer, Digital Design at Renesas Electronics. Skills: Logic design, micro-architecture, RTL coding, Verilog, System-Verilog, synthesis, timing analysis, STA, ATPG generation. Design of optimized digital blocks meeting functional, cost and low power constraints and ensure spec compliance. Develop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis”
What You'll Achieve.
ensure spec compliance; deliver on-time under a tight schedule; contribution to company goals
Industry & Context.
Develop work-around solutions where necessary to overcome device errata
Flexible to undertake occasional international travel at short notice
What They're Looking For.
Must Have
10+ years of relevant experience in Logic design /micro-architecture / RTL coding, Must have hands on experience with Power product design, synthesis and timing analysis for complex Analog Circuits, Experience in Verilog/System-Verilog is a must, Experience working in semiconductor ideally PMIC or Audio with focus on mixed signal integrated circuits, Hands on experience developing block and top-level timing constraints for STA and P & R sign off, Knowledge of scan insertion and ATPG generation, Understanding of design constraints and synthesis scripts
Nice to Have
Ability to propose innovative solutions, Results-oriented and able to deliver on-time under a tight schedule, Cross cultural awareness and sensitivity, Proactive attitude about own role and contribution to company goals, Ability to work both independently and part of a team, Flexible to undertake occasional international travel at short notice, Excellent command of verbal and written English
What You'll Do.
Design of optimized digital blocks meeting functional
cost and low power constraints and ensure spec compliance
Develop TCL scripts and design constraints to perform synthesis
DFT insertion and static timing analysis
Support DFT strategy and implementation
Verification planning
feature extraction and verification test case development
Interface with P & R for digital hand-off and post layout verification
Develop test vectors for production test
Perform physical silicon device evaluation where necessary
Produce high quality documentation for own blocks
Develop work-around solutions where necessary to overcome device errata including documentation
How You'll Work.
Team & Collaboration
Interface with P & R for digital hand-off and post layout verification; Ability to work both independently and part of a team
Communication Scope
Excellent command of verbal and written English
Process & Methodology
Results-oriented and able to deliver on-time under a tight schedule
Full Job Description
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Principal Accountabilities: * Design of optimized digital blocks meeting functional, cost and low power constraints and ensure spec compliance. * Develop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis. * Support DFT strategy and implementation. * Verification planning, feature extraction and verification test case development. * Interface with P & R for digital hand-off and post layout verification. * Develop test vectors for production test. * Perform physical silicon device evaluation where necessary. * Produce high quality documentation for own blocks. * Develop work-around solutions where necessary to overcome device errata including documentation. * All other tasks as deemed reasonable by your manager
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