OLIX
AI
Senior/StaffDigitalDesignEngineer
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“Senior/Staff Digital Design Engineer at OLIX. Skills: CMOS digital design, high-speed, real-time data-processing silicon design, FPGA prototyping, RTL development, EDA flows. Architect, design and implement high-throughput digital pipelines. Prototype and iterate rapidly in FPGA”
What You'll Achieve.
take end‑to‑end ownership of high‑speed, real‑time data‑processing silicon; achieve aggressive bandwidth‑per‑watt targets
Industry & Context.
closing timing on multi-hundred-MHz to multi-GHz clock domains; achieve aggressive bandwidth-per-watt targets
Due to U. S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.
What They're Looking For.
Must Have
7+ years of hands-on digital design for high-performance ASICs or SoCs, including ownership of at least one product that processes a continuous real-time data stream, Proven success closing timing on multi-hundred-MHz to multi-GHz clock domains and integrating high-speed IP (e. g. , SerDes, HBM/DDR, PCIe, 100 GbE or similar), Expertise with industry-standard EDA flows: RTL synthesis, CDC/RDC, STA, power-intent (UPF/CPF), lint, and gate-level simulation, Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab, Solid grounding in digital signal-processing concepts, computer-architecture fundamentals and semiconductor device physics
Nice to Have
Tape-out experience at 22 nm or below, Knowledge of coherent optical links or photonic-electronic co-design, Familiarity with AI/ML workloads, systolic arrays or tensor-processing architectures, Contributions to open-source RTL, verification frameworks or FPGA boards
What You'll Do.
design and implement high-throughput digital pipelines
Prototype and iterate rapidly in FPGA
Model algorithms and validate concepts
performance and area (PPA)
Implement innovative techniques to achieve aggressive bandwidth-per-watt targets
How You'll Work.
Team & Collaboration
Collaborate with optical-hardware, mixed-signal and software teams; cross-functional collaboration
Communication Scope
Excellent communication
Process & Methodology
lead design reviews
Full Job Description
ABOUT OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance. THE ROLE We are seeking highly skilled and motivated Senior/Staff Digital Design Engineers with a strong focus on CMOS digital design to take end‑to‑end ownership of high‑speed, real‑time data‑processing silicon—from early algorithm modelling to verified RTL and silicon bring‑up. You will join a multidisciplinary group creating next‑generation hardware where digital, optical and mixed‑signal domains intersect. The ideal candidate will have a strong background in electrical engineering and semiconductor physics, along with a passion for developing reliable, high-performance digital circuits that drive breakthrough AI hardware. RESPONSIBILITIES - Architect, design and implement high‑throughput digital pipelines (multi‑GSPS input rate, continuous streaming data paths, deep pipelining and hand‑shaking) in advanced CMOS nodes. - Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‑up real‑time demos, exercise high‑speed transceivers, and feed learnings back into the ASIC. - Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‑level sign‑off. - Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static‑timing closure, formal and constrained‑random verification. - Analyse
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