Analog Devices
semiconductor
SeniorSTAengineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Senior STA engineer at Analog Devices. Skills: Timing Constraints Development, Timing Analysis and Closure, Power Optimization, Digital Synthesis. lead block-level digital design synthesis. lead STA efforts”
What You'll Achieve.
achieve timing closure; optimize for power efficiency
Industry & Context.
solve complex QoR challenges; root cause of timing violations issues; suggest solutions; troubleshooting skills
10% of the time travel
What They're Looking For.
Must Have
Digital Synthesis, DFT insertion, Check Design, Check Timing Analysis, complex digital systems timing closure, power optimization, digital design implementation methodologies, solve complex QoR challenges, achieve timing closure of block & full chip, Timing Constraints Development, Timing Analysis and Closure, Power Optimization, Strong troubleshooting skills, STA and Signoff of complex high speed SoC designs, cutting edge process technologies (16nm and below), Timing ECOs driven by tool and manual ECO techniques, Scan/DFT modes and timing, digital flow design aspects RTL to GDS, tcl/perl/python scripts, automation on timing analysis tools, Flow enhancements to resolve timing and/or timing-DRC issues
Nice to Have
Floor-planning, Placement, CTS, Routing using physical design tools, Extraction, Physical Verification, EM/IR flows, Signoff checks
What You'll Do.
lead block-level digital design synthesis
responsible for complex digital systems timing closure
responsible for power optimization
mentor junior engineers
solve complex QoR challenges
achieve timing closure of block & full chip
develop complex timing constraints
root cause of timing violations issues
suggest solutions across various stages
STA and Signoff of complex high speed SoC designs
enhance flows to resolve timing issues
How You'll Work.
Team & Collaboration
working with designers; cross-collaborative environment
Communication Scope
Good communication skills
Full Job Description
**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). **Senior Digital Design Engineer** **About the Role** As a Senior Digital Design Engineer, you will lead block-level digital design synthesis and STA efforts. You'll be responsible for complex digital systems timing closure, and power optimization while mentoring junior engineers. This position requires deep understanding of digital design implementation methodologies, solve complex QoR challenges and achieve timing closure of block & full chip. **Key Responsibilities** * Hands on experience in Digital Synthesis, DFT insertion, Check Design and Check Timing Analysis * Good understanding of all aspects of liberty models including power * Ability to develop complex timing constraints by working with designers is a must. Should have experience in IP/subsystem/full-chip timing constraints * Knowledge of commands and constructs supported across synthesis, STA , LEC and PD tools * Analysis skills to root cause of timing violations issues and suggest solutions across various stages of design Implementation * Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below). * Strong expertise in Timing ECOs driven by tool and manual ECO techniques for timing closu
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