Micron Technology
Semiconductor
SeniorSOCPhysicalDesignEngineer,HBM
Neural analysis suggests this role is
optimal for Senior candidates.
“Senior SOC Physical Design Engineer, HBM at Micron Technology. Skills: Physical design, SoC integration, HBM, Timing closure. Support physical implementation of SoC blocks. Meet performance, power, area targets”
What You'll Achieve.
Deliver best-in-class PPA; Deliver robust signoff collateral; See work through tapeout; See work through silicon
Industry & Context.
Debug timing violations; Debug DRC violations; Debug LVS violations; Post-silicon debug
What They're Looking For.
Must Have
Hands-on EDA tools experience, Static timing analysis fundamentals, Clocking concepts, Synopsys Design Constraints (SDC), Power intent methodologies, Unified Power Format (UPF), Common Power Format (CPF), Power grid planning, Physical verification flows, Signoff flows, Design rule checking, Layout versus schematic, Parasitic awareness, Hierarchical physical design, SoC integration methodologies
Nice to Have
HBM or DRAM adjacent SoC designs, Memory-subsystem-heavy SoCs, Signal integrity analysis, Reliability analysis, IR drop analysis, Electromigration analysis, Tcl script development, Python script development
What You'll Do.
Support physical implementation of SoC blocks
Assist with setup and hold timing closure
Collaborate with RTL design teams
Ensure correct clocking
Ensure reset strategies
Ensure power intent implementation
Integrate complex IP blocks
Implement complex IP blocks
Focus on timing correctness
Focus on physical correctness
Run physical signoff checks
Debug physical signoff checks
Address DRC violations
Address LVS violations
Address timing violations
Ensure scan logic is clean
Ensure MBIST logic is clean
Participate in tapeout readiness activities
Perform engineering change order flows
Perform design reviews
Perform post-silicon debug
Correlate silicon behavior
Apply EDA tool experience
Work in cross-functional team
How You'll Work.
Team & Collaboration
Design teams; Verification teams; DFT teams; Packaging teams; Manufacturing teams; RTL design teams; Cross-functional team; Global team
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. You will drive physical implementation of advanced high‑bandwidth memory (HBM) system‑on‑chip (SoC) logic and base die designs from netlist through GDSII within the Heterogeneous Integration Group. You will collaborate closely with design, verification, design for test (DFT), packaging, and manufacturing teams to deliver best‑in‑class performance, power, and area (PPA) with robust signoff collateral. This is a hands‑on role where you can own blocks or top‑level integration across multiple product generations and see your work through tapeout and silicon. Job Description ### Responsibilities will include, but are not limited to: * Support physical implementation of SoC blocks from floorplanning through placement, clock tree synthesis (CTS), routing, and optimization to meet performance, power, and area targets. * Assist with setup and hold timing closure across multi‑mode, multi‑corner (MMMC) scenarios using industry tools such as PrimeTime or Tempus under guidance of senior engineers. * Collaborate with RTL design and integration teams to ensure correct clocking, reset strategies, and power intent implementation throughout the design. * Integrate and implement complex intellectual property (IP) blocks including controllers, interfaces, memory built‑in self‑test (MBIST), design for test (DFT) logic, buffers, and PHY‑adjacent logic with focus on timing and physical correctness. * Run and debug physical signoff checks such as design rule checking (DRC), layout versus schematic (LVS), and timing signoff, addressing violations with support from signoff experts. * Work with DFT teams to ensure scan and MBIST logic are physically clean and do not negatively impact timin
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