NVIDIA
artificial intelligence
SeniorPowerIntegrityCoDesignEngineer
“Senior Power Integrity Co-Design Engineer at NVIDIA. Skills: Power Integrity, Co-Design, di/dt mitigation, voltage noise targets, PDN design, Sim-to-Si correlation, AI techniques for power integrity. Define product-level voltage noise targets, drive them to closure, and sign them off at shipment.. Architect voltage noise mitigation across the full stack - silicon, package, board, platform - and lead the codesign tradeoffs between them.”
Industry & Context.
address sophisticated challenges; systems thinking; rigorous engineering judgment; Sim-to-Si correlation instincts — the rigor of knowing which side of the equal sign is wrong, and the independence to say so.; Clear judgment is required to know where the model is conscientious and where manual measurement is vital.
What They're Looking For.
Must Have
BS, MS, or PhD in EE, CE, or related (or equivalent experience) with 12+ years in silicon power integrity, voltage noise, or PDN, Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, or decap budgeting., Hands-on silicon experience: bring-up, characterization, correlation — comfortable on a bench with scopes, probes, and DAQ, and in front of a simulator., Sim-to-Si correlation instincts, Proven use of AI techniques to accelerate power integrity work includes noise modeling, transient prediction, Sim-to-Si analysis, and automated correlation checks., Multi-functional collaboration and spec subject area: able to drive a decision through multiple partners, detail it, and own it through sign-offs.
Nice to Have
Proof of craft: patents, publications, or reusable methodology you built in power integrity, PDN, or di/dt, Hands-on experience with groundbreaking GPU, CPU, or AI accelerator silicon at advanced multi-rail, multi-domain PDN ownership at SoC level (die + package + board co-optimization in production)., A track record of applying ML or AI to noise modeling, transient prediction, droop response, or feature optimization — with the validation rigor to know when the model is wrong.
What You'll Do.
Define product-level voltage noise targets
drive them to closure
and sign them off at shipment.
Architect voltage noise mitigation across the full stack - silicon
platform - and lead the codesign tradeoffs between them.
Co-design noise features with Speed/Power/Reliability
Build and lead the Sim-to-Si correlation methodology for voltage noise.
Model and prototype next-gen noise features - transient sense
Lead show-stopper noise bugs during bringup.
Drive architecture-level codesign tradeoffs across V/F ↔ Power ↔ Noise ↔ Reliability ↔ Thermal boundary work.
How You'll Work.
Team & Collaboration
Co-design noise features with Speed/Power/Reliability, circuit, power-arch, ASIC, and platform teams.; You're the connective tissue across the codesign web.; able to drive a decision through multiple partners, detail it, and own it through sign-offs.
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