NVIDIA

Accelerated computing

SeniorPowerAnalysisandOptimizationEngineer

$136–265k Santa Clara, California, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior Power Analysis and Optimization Engineer at NVIDIA. Skills: Power Analysis, AI, Machine Learning, LLMs. Analyze power using tools. Translate data into improvements”

Industry & Context.

Accelerated computing
Problems you'll solve

Root-cause power bugs; Identify trends, anomalies, and optimization opportunities

What They're Looking For.

Must Have

MS (or equivalent experience) and 5yrs experience OR PHD + 3yr experience in EE/CE/CS or related fields, understanding of energy consumption, power estimation, data movement, and low-power design, Familiarity with Verilog and ASIC design principles, hands-on experience with tools such as PowerArtist, PrimePower/PrimePower RTL, RTL Architect, or similar, Solid coding and automation skills, preferably in Python, Perl, and C++, Experience or interest in machine learning, reinforcement learning, and data analytics, ideally applied to EDA, architecture, or system-level optimization, Interest or experience in building and using LLMs or other foundation models as engineering copilots—especially for EDA/power/architecture workflows, Excellent communication and collaboration skills to work effectively with cross-functional design and architecture teams, A genuine desire to bring data-driven, AI-assisted decision-making into power architecture and help shape the energy profile of NVIDIA’s future products

What You'll Do.

Analyze power using tools

Translate data into improvements

Develop power-aware models

Design and train LLMs

Assist engineers with data

Recommend optimizations

Perform comparative analysis

Prototype new features

Automate and scale flows

Apply AI to power optimization

Tune power-efficient configurations

How You'll Work.

Team & Collaboration

Partner closely with Architects, Performance, Software, ASIC Design, and Physical Design teams

Communication Scope

Excellent communication and collaboration skills

Full Job Description

We’re looking for a Senior Power Architecture & Optimization Engineer to push the limits of energy efficiency using advanced analytics and AI, including LLMs trained specifically for power analysis. NVIDIA’s leadership in accelerated computing depends on building the most energy‑efficient GPUs and SoCs in the industry. As AI and graphics workloads scale explosively, we believe that Power Analysis and Optimization driven by AI and LLMs is the future—and a key differentiator for our next generations of GPUs and Tegra SoCs. In this role, you’ll be at the center of that effort—combining power architecture expertise with machine learning, reinforcement learning, data analytics, and large language models (LLMs) to invent new ways to model, analyze, and optimize energy consumption across full‑chip and unit‑level designs. **What You’ll Be Doing:** * Analyze full‑chip and unit‑level power using internal and industry‑standard RTL and gate‑level power tools, and translate data into concrete design and architectural improvements. * Develop and productionize power‑aware models and flows, including ML/RL‑based techniques for anomaly detection, dynamic power management, and design‑space exploration. * Design and train new LLMs that “learn the art” of power analysis from design data, power reports, bug histories, and best practices—so they can: * Assist engineers in interpreting complex power data * Propose likely root causes and candidate fixes * Recommend architectural and micro‑architectural optimizations for power * Perform comparative power analysis across workloads, products, and design options to identify trends, anomalies, and optimization opportunities that aren’t obvious from first principles alone. * Partner closely with Architects, Performance, Software, ASIC Design, and Physical Design teams to interpret power data, root‑cause power bugs, and drive fixes and design changes. * Prototype and evaluate new architectural features in Verilog, with a strong focus on their pow

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