SeniorPostSiliconLowPowerIntegrationEngineer

NVIDIA Silicon Co-Design Group is looking for a versatile engineer to help redefine how low-power silicon validation and system bring-up are developed for next-generation AI and accelerated computing platforms. Our team sits at the intersection of silicon architecture, platform validation, firmware, telemetry, and productization. We build the methodologies, infrastructure, and workflows that take low-power features from architectural intent through silicon bring-up and into production readiness. This role is about scaling low-power validation using AI-powered analytics, intelligent automation, telemetry pipelines, and modern debug workflows. You will help transform how power validation, workload characterization, feature correlation, and silicon debug are accomplished across product generations. The payoff is that the systems, tooling, and methodologies you help build will directly influence the power efficiency, stability, and production readiness of NVIDIA products shipped at scale worldwide. **What You 'll Be Doing:** * Define the Power & Performance validation strategy across product lines, including power targets, rail budgets, and low-power feature validation methodologies. * Build intelligent workload characterization frameworks that use telemetry, behavioral clustering, and AI-assisted analytics to improve validation coverage and expose power-state and data-path issues earlier in the development cycle. * Define the instrumentation, counters, telemetry frameworks, and firmware hooks needed to support scalable silicon observability, automated validation, and AI-powered debug workflows prior to tapeout. * Bring up and validate system-level low-power features across pre-silicon and post-silicon environments using sophisticated automation, data-driven validation methodologies, and generative AI-assisted debug techniques. * Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, autom