NVIDIA
Networking Silicon
SeniorPhysicalDesignVerificationLayoutEngineer
“Senior Physical Design Verification Layout Engineer at NVIDIA. Skills: Physical Design, Physical Verification, Layout. Chip floorplan and pin placement. Integration within innovative builds”
What You'll Achieve.
Ensuring integration within our innovative builds; Ensuring strict adherence to our high standards; Contributing to the development of our groundbreaking chips; Delivering the highest throughput and lowest latency
Industry & Context.
What They're Looking For.
Must Have
B. SC. / M. SC. in Electrical Engineering, 5+ years of hands-on layout experience, Physical Verification methodology, including ERC, LVS and DRC, In-depth knowledge of advanced silicon process technologies, Familiarity with physical build EDA tools, including Synopsys and Cadence, A great teammate who thrives in a collaborative environment, AI tools orientation or alternatively a desire to learn
Nice to Have
Experience in Linux environments, TCL, Python, shell scripting abilities, Experience with data collection and analysis, Understanding of the chip and die verification process
What You'll Do.
Chip floorplan and pin placement
Integration within innovative builds
and approve Physical Verification flows
Perform physical layout implementation
planning and optimization
How You'll Work.
Team & Collaboration
Thrives in a collaborative environment
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