NVIDIA

Networking Silicon

SeniorPhysicalDesignMethodologyEngineer,PPAFusionCompiler

$168–311k Santa Clara, California, United States FULL TIME Remote Friendly
The Brief

“Senior Physical Design Methodology Engineer, PPA Fusion Compiler at NVIDIA. Skills: Physical Design Methodology, PPA Fusion Compiler, ML-based solutions. Developing Efficient physical design methodologies for implementation of graphics processors and SOCs. developing unique and creative solutions to the state-of-the-art physical design problems to improve PPA”

What You'll Achieve.

improve PPA; highest throughput and lowest latency

Industry & Context.

Networking Silicon
Problems you'll solve

algorithmic solutions

What They're Looking For.

Must Have

MS in Electrical, Computer Engineering, computer science (or equivalent experience), 10+ years’ experience in Physical Design Engineering, ML based solution development experience, Proven implementation of ML-based solutions, Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification, Staring knowledge of Physical design with convergence in timing/IR with best PPA, background with hierarchical design approach, top-down design, budgeting, timing and physical convergence, Familiar with various process related design issues including Design for Yield and Manufacturability, and IR closure and thermal management, Solid understanding of standard industry PnR tools and analysis tools, Capable of extensive scripting to check and improve PPA

What You'll Do.

Developing Efficient physical design methodologies for implementation of graphics processors and SOCs

developing unique and creative solutions to the state-of-the-art physical design problems to improve PPA

formulate and develop with ML-based solutions

developing flow and tool methodologies for P&R

timing analysis and closure

convergence in IR/Signal-EM

power and noise analysis and back-end verification across multiple projects along with chip floorplan

power and clock distribution

Data based analysis and algorithmic solutions for PPA check and improvement

Free ATS check

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