SeniorPhysicalDesignEngineer–DPGLayout

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Role and Responsibilities** * Execute physical design implementation for SoC blocks and large digital sub-blocks, including floorplanning support, placement, CTS, routing, and physical optimization, to meet power, performance, and area (PPA) targets. * Drive block-level timing closure (setup/hold) across multi-mode, multi-corner (MMMC) scenarios, working closely with STA, RTL, and integration teams to resolve timing issues efficiently. * Implement and debug clocking, reset, and power intent (UPF/CPF) for assigned blocks, ensuring correctness and alignment with SoC integration requirements. * Perform physical verification and signoff checks, including DRC/LVS, antenna, IR drop, EM, noise, and timing, and systematically resolve violations with guidance from senior or staff engineers. * Support tape-out activities through ECO implementation, closure tracking, signoff reviews, and documentation, ensuring deliverables meet quality and schedule expectations. * Collaborate with CAD, methodology, and technology teams to debug PD tool or flow issues and adopt approved methodologies for advanced nodes. * Contribute to productivity and quality improvements by developing scripts, automation, or checks that reduce manual effort and improve turnaround time. * Participate in design and build reviews, sharing learnings, best practices, and root-cause analyses from implementation and signoff cycles. * Assist in post-silicon debug by correlating layout, timing, and power analysis with silicon observations when required. **Job Requirements** * 6+ years of hands-on experience in physical design implementation for complex SoCs or large digital blocks. * Strong experience with block