NVIDIA
AI
SeniorPhysicalDesignEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Senior Physical Design Engineer at NVIDIA. Skills: Physical Design, Timing Closure, Physical Verification. Drive physical design and timing from netlist to gds. Integrate Analog IO’s and macros”
Industry & Context.
Tackle hard opportunities
What They're Looking For.
Must Have
BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years' experience or MS (or equivalent experience) with 2+ years' experience in physical design, Experienced in Synopsys or Cadence place and route, physical design and timing tools, Ability to form methodologies and automate flows
Nice to Have
Scan insertion and DFT knowledge is a plus
What You'll Do.
Drive physical design and timing from netlist to gds
Integrate Analog IO’s and macros
Perform multi-mode and multi-corner timing closure
Create and update timing constraints
Perform Physical verification (DRC
Antenna checks and other checks)
Debug timing violations
Perform formal verification
How You'll Work.
Team & Collaboration
Partner with mixed signal teams; Work with the Front-end teams
Full Job Description
We are now looking for a motivated Physical Design Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence. **What you 'll be doing:** * Drive physical design and timing from netlist to gds. * Partner with mixed signal teams to integrate Analog IO’s and macros. * Work on multi-mode and multi-corner timing closure, RC extraction, Cross talk, IR drop and EM analysis. * Work with the Front-end teams to create and update timing constraints. * Perform Physical verification DRC, ERC, LVS, Antenna checks and other checks. * Debugging timing violations and implementing functional, Timing ECO’s and perform formal verification. **What we need to see:** * BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years' experience or MS (or equivalent experience) with 2+ years' experience in physical design. * Experienced in Synopsys or Cadence place and route, physical design and timing tools. * Ability to form methodologies and automate flows. * Scan insertion and DFT knowledge is a plus Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and [benefits](https://www.nvidia.com/en-us/benefits/). Applications for this job will be accepted at least until May
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