NVIDIA
Semiconductor
SeniorPhotonicLayoutDesignEngineer
“Senior Photonic Layout Design Engineer at NVIDIA. Skills: Photonic Layout Design, Silicon Photonics (SiPh), Physical Design, Verification, Layout Automation. Ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs). Guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness”
What You'll Achieve.
Achieve high-yield manufacturing goals
Industry & Context.
Trace defect sources; Mitigate layout-dependent issues; Ensure DRC/LVS cleanliness
What They're Looking For.
Must Have
Deep technical understanding of advanced node semiconductor fabrication, Sophisticated automation capabilities, Proven track record of first-time success on high-density chip designs, At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries, Deep understanding of analog circuit layout, Deep understanding of Silicon Photonic constraints, Deep understanding of device physics within advanced sub-micron CMOS and SiPh technologies, Proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows, Ability to optimize workflows using best-known methods (BKMs), Proactively collaborate with integration, and design rule teams to achieve high-yield manufacturing goals
Nice to Have
AI-assisted design methods, layout automation scripts, custom Pcells
What You'll Do.
Ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs)
Guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness
full-loop manual and automated layout designs for waveguides
and mixed-signal functions
Drive the full tape-out process
including floor planning
and mask data preparation
Execute rigorous post-layout verification (DRC
density) across multiple stepping versions
mitigate layout-dependent issues
and ensure DRC/LVS cleanliness prior to tape-out
Own the layout of complex test structures
active/passive full loops
and certification vehicles with large Design of Experiments (DOEs) to optimize for process windows
Develop and implement AI-assisted design methods
layout automation scripts
and custom Pcells to improve productivity
reduce development cycle times
and customize DRC/LVS checking flows
How You'll Work.
Team & Collaboration
Work within a highly collaborative, multidisciplinary team of photonics, CMOS, packaging, and systems engineers; Proactively collaborate with integration, and design rule teams
Process & Methodology
Ownership of the physical design and verification, Guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness, Lead complex, full-loop manual and automated layout designs, Drive the full tape-out process, Own the layout of complex test structures, Develop and implement AI-assisted design methods
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