NVIDIA

Semiconductor

SeniorPhotonicLayoutDesignEngineer

$132–236k Santa Clara, California, United States FULL TIME Remote Friendly
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior Photonic Layout Design Engineer at NVIDIA. Skills: Photonic Layout Design, Silicon Photonics (SiPh), Cadence Virtuoso, Verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield), Programming and scripting languages (Python, SKILL, Perl, TCL, or C++). Ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs). Guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness”

What You'll Achieve.

Achieve high-yield manufacturing goals; Improve productivity; Reduce development cycle times

Industry & Context.

Semiconductor
Problems you'll solve

Trace defect sources; Mitigate layout-dependent issues

What They're Looking For.

Must Have

Deep technical understanding of advanced node semiconductor fabrication, Sophisticated automation capabilities, Proven track record of first-time success on high-density chip designs, At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries, Deep understanding of analog circuit layout, Deep understanding of Silicon Photonic constraints, Deep understanding of device physics within advanced sub-micron CMOS and SiPh technologies, Proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows, Ability to optimize workflows using best-known methods (BKMs), Proactively collaborate with integration, and design rule teams to achieve high-yield manufacturing goals

Nice to Have

AI-assisted design methods, layout automation scripts, custom Pcells

What You'll Do.

Ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs)

Guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness

full-loop manual and automated layout designs for waveguides

and mixed-signal functions

Drive the full tape-out process

including floor planning

and mask data preparation

Execute rigorous post-layout verification (DRC

density) across multiple stepping versions

mitigate layout-dependent issues

and ensure DRC/LVS cleanliness prior to tape-out

Own the layout of complex test structures

active/passive full loops

and certification vehicles with large Design of Experiments (DOEs) to optimize for process windows

Develop and implement AI-assisted design methods

layout automation scripts

and custom Pcells to improve productivity

reduce development cycle times

and customize DRC/LVS checking flows

How You'll Work.

Team & Collaboration

Work within a highly collaborative, multidisciplinary team of photonics, CMOS, packaging, and systems engineers; Proactively collaborate with integration, and design rule teams

Process & Methodology

Layout Execution & Tape-out Ownership, Verification & Mitigation, Test Vehicle & Component Development, Automation & AI-Assisted Workflows

Full Job Description

Are you seeking an outstanding opportunity? We are looking for a Senior Photonic Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal & Silicon Photonic Designs! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Join our diverse team today! **What You 'll Be Doing:** * As a Senior Photonics Layout Engineer, you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness. You will work within a highly collaborative, multidisciplinary team of photonics, CMOS, packaging, and systems engineers to drive next-generation Silicon Photonics (SiPh) and SERDES products. * Layout Execution & Tape-out Ownership: Lead complex, full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions (high-speed/general I/Os, ESD structures). Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation. * Verification & Mitigation: Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions. Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out. * Test Vehicle & Component Development: Own the layout of complex test structures, active/passive full loops, and certification vehicles with large Design of Exp

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