NVIDIA
SeniorPerformanceModelingArchitect,CPUFabricandLLC
“Senior Performance Modeling Architect, CPU Fabric and LLC at NVIDIA. Skills: Performance Modeling, CPU Cache Hierarchies, Interconnects, C++, SystemC, Python. Developing and maintaining high-fidelity, cycle-accurate performance models (C++/SystemC) for coherent interconnects and large-scale shared caches. Modeling and analyzing performance bottlenecks across varying scales, from small-cluster automotive SoCs to massive, multi-mesh data center architectures”
What You'll Achieve.
achieve ambitious performance goals
Industry & Context.
architectural trade-offs
What They're Looking For.
Must Have
Master’s or Ph. D. in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience) with a focus on architecture, 5+ years of experience, understanding of CPU microarchitecture, memory consistency models, and cache coherency protocols, Proven experience in C++ or SystemC for cycle-accurate or functional modeling, Proficiency in Python or similar scripting languages for processing large datasets, generating performance visualizations, and automating simulation sweeps, Understanding of Network-on-Chip (NoC) topologies (Mesh, Ring, Torus), credit-based flow control, and arbitration logic
Nice to Have
Practical experience managing the functional safety (ISO 26262) requirements of automotive chips alongside the power-performance-area (PPA) limitations of data center hardware, Experience defining or using PMU (Performance Monitoring Unit) events to debug performance on real silicon or emulators, A background in using formal verification or mathematical modeling to prove the correctness of complex coherency state machines, A history of building your own internal tools or frameworks to accelerate architectural exploration rather than just using off-the-shelf simulators, Knowledge of emerging memory technologies like CXL (Compute Express Link) or HBM (High Bandwidth Memory) and how they collaborate with coherent fabrics
What You'll Do.
Developing and maintaining high-fidelity
cycle-accurate performance models (C++/SystemC) for coherent interconnects and large-scale shared caches
Modeling and analyzing performance bottlenecks across varying scales
from small-cluster automotive SoCs to massive
multi-mesh data center architectures
Evaluating the performance impact of different coherency protocols (e. g.
or proprietary) and snooping filters
Running and analyzing industry-standard benchmarks (SPEC
Automotive-specific suites) to drive architectural trade-offs
How You'll Work.
Team & Collaboration
Collaborating with build and verification teams to correlate performance models with silicon; working with software teams to optimize drivers for the underlying hardware topology
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