NVIDIA

Technology

SeniorPackageLayoutEngineer

Bengaluru, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior Package Layout Engineer at NVIDIA. Skills: Senior Package Layout Engineer, IC substrates design, high speed/density ASIC packages implementation, substrate breakout patterns, package routing, Cadence APD or SiP tool suite. implement high speed/density ASIC packages. Perform substrate breakout patterns for ASIC packages”

What You'll Achieve.

making a difference in the world through their contributions; deliver new and creative, unusual solutions to extraordinary problems

Industry & Context.

Technology
Problems you'll solve

resolve costs, manufacturing, and electrical design issues; design feasibility studies to evaluate the Package design goals for size, cost, and system performance

What They're Looking For.

Must Have

5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology, B. S. Electrical Engineering or equivalent experience, Solid understanding of high-speed design signal integrity practices

Nice to Have

Experience with HDI designs is a plus, Proven experience in substrate layout of wire bond and flip chip packages, Experience with Virtuoso and Calibre is a plus, Experience using Valor is helpful

What You'll Do.

implement high speed/density ASIC packages

Perform substrate breakout patterns for ASIC packages

Optimize package pinout incorporating system level trade-offs of pins assignment

perform package routing

reference plane and power distribution

Propose layout design trade-offs

Conduct design feasibility studies

Develop symbols and CAD library databases

Develop methodologies to improve layout productivity

How You'll Work.

Team & Collaboration

collaborate to implement high speed/density ASIC packages; collaborate with Technical Package Lead; work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues; Propose layout design trade-offs to the Technical Package Lead for resolution and implementation

Process & Methodology

planning schedules

Full Job Description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. **What you 'll be doing:** * As part of a Layout team, you will collaborate to implement high speed/density ASIC packages. * Perform substrate breakout patterns for ASIC packages. * Optimize package pinout incorporating system level trade-offs of pins assignment. * Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite. * Propose layout design trade-offs to the Technical Package Lead for resolution and implementation. * Conduct design feasibility

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