Micron Technology

Semiconductor

SeniorPackageDesignEngineer

$145–210k ~AI est. Boise, Idaho, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior Package Design Engineer at Micron Technology. Skills: Package design, Memory products, Co-design activities, Substrate design. Lead co-design activities. Define new product concepts”

What You'll Achieve.

Deliver high-performance package designs; Deliver reliable package designs; Deliver manufacturable package designs; Deliver scalable package solutions; Meet electrical requirements; Meet mechanical requirements; Meet thermal requirements; Meet reliability requirements; Advance designs for performance; Advance designs for manufacturability; Advance designs for reliability; Ensure designs meet vendor specifications; Ensure designs meet HVM specifications

Industry & Context.

Semiconductor
Problems you'll solve

Design optimization; Feasibility studies; DFM reviews; DFMEA reviews

What They're Looking For.

Must Have

Master's degree in EE, ME, Materials Science, or related field with 5+ years of industry experience in advanced memory substrate design, Bachelor's degree in a related field with 10+ years of industry experience in advanced memory substrate design, Hands-on proficiency with industry-standard EDA tools, Experience in advanced memory substrate design, Demonstrated experience partnering with SI and PI teams, Experience collaborating with OSAT partners, assembly engineering teams, and multi-functional global organizations

Nice to Have

10+ years of industry experience in semiconductor package design, Experience with TSV-based stacking, Experience with micro-bump layout, Experience with Chip Package Interaction (CPI) analysis, Experience leading co-design engagements, Experience with Assembly DOE definition and management, Experience with DFMEA reviews, Experience with process/material development in HVM environment, Proficiency with mechanical drawing tools, Familiarity with advanced packaging platforms, Familiarity with associated design and manufacturing ecosystems

What You'll Do.

Lead co-design activities

Define new product concepts

Optimize die floorplans

Define interconnection schemes

Define package architectures

Optimize package architectures for DRAM products

Define substrate stack-up

Define wire bond interconnect schemes

Define flip chip interconnect schemes

Define BEOL/RDL flows

Lead package layout activities

Perform floorplanning

Perform high-density routing

Generate design databases

Maintain design databases

Generate package drawings

Maintain package drawings

Generate wire bond diagrams

Maintain wire bond diagrams

Generate interposer drawings

Maintain interposer drawings

Generate manufacturing documentation

Maintain manufacturing documentation

Partner with electrical teams

Partner with simulation teams

Interpret parasitic modeling data

Interpret validation data

Drive design optimization

Drive material selection

Conduct feasibility studies

Assess designs for performance

Assess designs for manufacturability

Assess designs for reliability

Partner with SI teams

Partner with PI teams

Incorporate simulation analysis

Incorporate feedback into package architecture

Incorporate feedback into design optimization

Collaborate with assembly engineering

Collaborate with internal sites

Collaborate with OSAT partners

Collaborate with subcontractor partners

Conduct package reviews

Conduct DFMEA reviews

Ensure designs meet vendor specifications

Ensure designs meet HVM specifications

Work with SBT suppliers

Work with Technology Development

Work with Package Architecture teams

Advance routing methodologies

Support continuous improvement initiatives

Support global design alignment

Support package design rule system development

Support competitive analysis

Support package roadmaps

Support IP development

How You'll Work.

Team & Collaboration

Global multi-functional teams; Silicon design teams; Business Units; Customers; Customer-facing teams; Package architecture teams; Product architecture teams; Technology Development; Simulation teams; Manufacturing teams; Assembly engineering; Internal assembly sites; External OSAT partners; SBT suppliers

Full Job Description

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Global Design, Simulation, and Substrate team at Micron Technology is a world-class group of engineers developing advanced semiconductor packaging solutions for memory products including DRAM and NAND. The team operates globally, collaborating with internal assembly sites, technology development teams, and external OSAT partners to deliver high-performance, reliable, and manufacturable package designs across Micron's product portfolio! As a Senior Package Design Engineer, you will lead co-design activities that bridge silicon design, package architecture, and product development for advanced DRAM and memory products targeting applications such as Mobile, Automotive, Artificial Intelligence, Edge/Cloud Computing, and Data Center. During the co-design phase, you will partner with silicon design teams, Business Units, customer-facing teams, and package and product architecture teams to define and drive new product concepts from inception through High Volume Manufacturing (HVM). Be part of the team! You will collaborate with global, multi-functional teams — including Package Architecture, Technology Development, simulation, and manufacturing — to deliver scalable, high-performance package solutions that meet electrical, mechanical, thermal, and reliability requirements. ## Responsibilities * Lead co-design activities by partnering with silicon design teams, Business Units, customers, customer-facing teams, and package and product architecture teams to define new product concepts, optimize die floorplans, interconnection schemes, and package architectures from the earliest stages of chip development. * Define and optimize package architectures for DRAM products, i

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