NVIDIA
SeniorMaskDesignEngineer
“Senior Mask Design Engineer at NVIDIA. Skills: Mask Layout Design, mixed-signal circuit designs, submicron CMOS technologies, Cadence tools, DRC and LVS verification. Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools. Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products”
Industry & Context.
DRC mitigation
What They're Looking For.
Must Have
BS in Electrical Engineering (or equivalent experience), At least 6+ years of hands-on layout design experience, Deep understanding of analog circuit layout concepts in submicron CMOS technologies, Validated experience with Cadence custom circuit design tools - particularly virtuoso, Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield, Ability to work optimally in a team, Good interpersonal skills, Positive energy, Proficiency in scripting languages like perl, python, skill etc., Knowledge of DRC and LVS checking flows, Ability to customize DRC and LVS
What You'll Do.
Perform physical layout for mixed-signal functions like PLL's
high speed I/O circuits
ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools
Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
Verifying against design rules and schematics
How You'll Work.
Team & Collaboration
Working collaboratively and multi-functionally with a multi-disciplinary team of Photonics, CMOS, Electronics, and Systems engineers; Work with ASIC and mixed-signal engineers
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