NVIDIA
Silicon
SeniorManager,Test,Manufacturability,ReliabilityandQuality
“Senior Manager, Test, Manufacturability, Reliability and Quality at NVIDIA. Skills: Test, Manufacturability, Reliability & Quality (TMRQ) leadership, Production test development (SLT, BLT), System reliability stress (HTOL), Manufacturing issue closure, Field diagnostic test development, Root-cause analysis, Cross-functional failure resolution, Team leadership and development. Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack CR, and system reliability stress (HTOL) across eve”
What You'll Achieve.
Decisions show up in yield curves, production ramp, and customer escapes.; Improve cycle time, first-pass yield, test-time reduction, escape rate, and DPPM.; Prevent field escapes from recurring.; Improve quality through screening, process, and build changes.
Industry & Context.
Close the hardest multi-functional failures.; Resolve Vmin and binning escapes, performance shortfalls, and power anomalies.; Conduct root-cause analysis on returns and field escapes.; Solve problems no one else can solve.; Operate independently on hard, ambiguous problems.
What They're Looking For.
Must Have
12+ years in production test, system validation, post-silicon integration, or reliability engineering in a high-volume silicon environment, 5+ years in management, EE fundamentals across DFT, BIST, digital design, computer architecture, fault models and fault analysis, power and timing analysis, sampling, and statistics, Hands-on expertise across the production test stack (ATE, SLT, BLT), Control Run methodology, FinFET-class manufacturing processes, and PVTinning dependencies
Nice to Have
Background in GPU, CPU, AI accelerator, or other large-SoC programs, Applied AI tools in production test or debug workflows, Track record of building and retaining senior technical talent in a highly matrixed organization, including guiding first-line managers to become autonomous leaders, Ability to operate independently on hard, ambiguous problems—and collaborate clearly across functions
What You'll Do.
Own the technical execution and velocity of SLT
and system reliability stress (HTOL) across every GPU
and CPU silicon program.
Resolve Vmin and binning escapes
performance shortfalls
and power anomalies by driving root-cause across design
Own the WARs and productized fixes through to confirmation.
Convert raw integration signals into decision-ready options for executive leadership.
Establish operational objectives and refine closed-loop methodologies.
Take ownership of manufacturing issues at both platform and board levels.
Conduct root-cause analysis on returns and field escapes.
Use field signals to develop screening
and build changes that improve quality.
and retain your manager and lead engineers across multiple geographies.
How You'll Work.
Team & Collaboration
Lead a team of individual contributors and a first-line manager.; Drive root-cause across design, methodology, DFT, ATE, package, software/firmware, and manufacturing.; Collaborate clearly across functions.
Communication Scope
Give leadership the clarity to act.; Convert raw integration signals into decision-ready options.; Collaborate clearly across functions.
Process & Methodology
Keep programs moving., Own the technical execution and velocity., Manage production ramp., Manage QS/PS gates., Manage ramp-impacting risks.
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