Silvaco

Semiconductor IP and EDA

SeniorManager,EmbeddedMemory

$1200000–1800000k ~AI est. Da Nang, Vietnam FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for not-applicable candidates.

The Brief

“Senior Manager, Embedded Memory at Silvaco. Skills: Embedded memory design, Memory compiler architecture, Circuit design, Customer engagement. Lead architecture, circuit design, physical implementation. Define bitcell selection”

What You'll Achieve.

Hit aggressive PPA targets; Shape compiler capabilities; Improve PPA competitiveness; Ensure customer integration confidence; Deliver silicon-qualified compilers

Industry & Context.

Semiconductor IP and EDA
Problems you'll solve

Root-cause analysis; Issue resolution; What-if analysis; Sensitivity analysis; Architecture trade-offs

What They're Looking For.

Must Have

BS, MS, or PhD in EE, CE, or related, 10+ years embedded memory design, Production tapeouts of SRAM, Tapeouts of ROM, 1PRF, 2PRF, or DPRAM, Deep expertise in bitcell circuit design, Memory peripherals expertise, Self-timed paths expertise, Sense amplifier design expertise, Assist circuit techniques expertise, Hands-on experience multiple process nodes, FinFET or advanced sub-7nm nodes experience, Command of SPICE simulation, Statistical and Monte Carlo analysis command, Vmin/yield modeling command, Reliability (BTI/HCI) analysis command, Working knowledge memory compiler architecture, Working knowledge memory compiler automation, Hands-on experience DFT/scan tools, Hands-on experience power integrity signoff, Hands-on experience layout verification flows, Familiarity with RTL/Verilog modelling, Familiarity with testchip definition, Familiarity with silicon correlation, Familiarity with SDK/automation development, Proven team leadership experience, Direct management or technical lead role, Team of 6+ memory designers managed, Demonstrated success customer-facing technical roles, Presales experience, PPA negotiation experience, Integration support experience, Excellent written communication skills, Excellent verbal communication skills, Proficiency with scripting, Proficiency with Linux environments, Experience working with AI tools

Nice to Have

Experience leading memory compiler programs, Background low-power memory design, Experience multi-port memory architectures, Experience specialty memories, Prior experience presenting industry venues, Contributing to memory IP standards, Direct experience interfacing foundry partners

What You'll Do.

physical implementation

Define bitcell selection

Define peripheral architecture

Define redundancy and repair strategy

Define assist circuits

performance optimization

Own technical roadmap

Establish design methodology

Establish verification methodology

Establish signoff methodology

Lead SPICE/FastSPICE characterization

Lead statistical/Monte Carlo analysis

Lead physical verification

Lead silicon validation efforts

Lead team of memory design engineers

Mentor memory design engineers

Grow team of memory design engineers

Conduct technical reviews

Allocate engineering effort

Build culture of design rigor

Build culture of peer review

Build culture of methodology improvement

Serve as senior technical lead

Qualify opportunities

Present memory portfolio

Shape winning technical proposals

Translate customer SoC requirements

Define compiler specifications

Define PPA commitments

Partner with field application engineers

Partner with product management

Lead deep-dive technical workshops

Respond to detailed technical questionnaires

Respond to audit-style reviews

Build competitive benchmarks

Maintain competitive benchmarks

Drive what-if analysis

Drive sensitivity analysis

Translate PPA insights

Create customer-ready collateral

Act as primary technical point of contact

Lead technical reviews

Lead integration debug

Lead silicon correlation discussions

Drive root-cause analysis

Drive resolution of customer issues

Coordinate across design teams

Coordinate across characterization teams

Coordinate across CAD teams

Coordinate across product teams

Represent Silvaco in foundry meetings

Represent Silvaco at industry conferences

How You'll Work.

Team & Collaboration

Customer SoC requirements; Sales and FAEs; Product management; Customer architects; Foundry partners; Industry conferences

Communication Scope

Customer presentations; Technical proposals; Technical workshops; Customer collateral; Datasheets; Application notes; Technical white papers; Technical reviews; Silicon correlation discussions; Foundry meetings; Industry conferences

Process & Methodology

Roadmap planning, Schedule management, Dependency management, Risk management

Full Job Description

Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications. Our mission is to provide our customers and partners with outstanding mixed-signal, silicon-proven IPs, creating in the process a differentiating technology that sets your products apart. At Mixel, you will find an inspiring environment with a strong focus on technical innovation, people well-being, no layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, empathy, mutual trust, and respect. About the Role Silvaco is hiring a Memory Design Lead to drive the architecture, design, customer interface and delivery of our embedded memory compiler portfolio: single-port SRAM, ROM, single- and dual-port register files (1PRF, 2PRF), and dual-port RAM (DPRAM). You will lead a team of memory designers, set the technical direction across multiple process nodes, and serve as the senior technical voice in customer engagements — from early presales architecture discussions through PPA negotiation, integration support, and silicon qualification. This role blends deep technical leadership with direct customer impact. You will shape what our compilers can do, how competitive their PPA is, and how confidently our customers can integrate them into their SoCs. If you have built memory compilers in production, mentored design teams, and enjoy translating customer requirements into winning silicon, this is a high-leverage role at a fast-growing semiconductor IP and EDA company. Key Responsibilities Technical Leadership & Memory Design * Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM. * Define bitcell selection, peripheral architecture (decoders, sense amps, write drivers, IO, self-timing), redundancy a

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