SeniorLayoutEngineer-DPGLayout

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Role and Responsibilities** * Implement the design and physical implementation of analog, mixed‑signal, custom digital blocks and support full‑chip integration, using a combination of traditional layout expertise. * Own block‑level layout execution with strong focus on quality, turnaround time and design intent. * Perform layout verification activities, including DRC, LVS, Antenna checks, Yield and quality checks. * Deliver on‑time, high‑quality block‑level layouts under the guidance from senior engineers. * Use prompt‑based AI tools to Generate or refine SKILL/Python/TCL scripts, automate repetitive layout and verification tasks to reduce manual effort and improve layout consistency. * Support custom and digital layout integration, using semicustom tools to accelerate ECOs, alignment, and integration‑level updates. * Collaborate closely with Design, Verification, CAD, and senior layout engineers, clearly communicating layout status and risks. * Assist in reviewing sub‑block layouts from engineers developing their skills and share helpful techniques within the team. **Job Requirements** * 3+ year experience in analog/custom layout design in advanced CMOS process. * Hands‑on experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks. * Experience in layout of critical analog and mixed‑signal blocks like Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps * Exposure to memory layout environments, including DRAM, SRAM, CAM or OTP is desirable. * Solid understanding of analog layout fundamentals, including Matching and symmetry techniques electromigration,