NVIDIA
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SeniorICPackagingDesignEngineer
“Senior IC Packaging Design Engineer at NVIDIA. Skills: IC Packaging design, high-speed Interconnect systems, substrate layout, Cadence APD (Allegro) or SiP tools. implement high speed and PDN design for ASIC packages. Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools”
What You'll Achieve.
delivering and designing state of the art high-speed Interconnect systems
Industry & Context.
What They're Looking For.
Must Have
5+ years hands-on in Package/PCB Layout and outing including high speed design signal integrity practices, B. Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience, Cadence APD (Allegro) or SiP tools, substrate layout of wire bond and flip chip packages
Nice to Have
Knowledge in Ansys (SIwave, HFSS) or Cadence (Sigrity, PowerSI) simulation tools, Familiarity with Skill language (Cadence) and basic parsing abilities (Python/Perl/Shell-scripting)
What You'll Do.
implement high speed and PDN design for ASIC packages
pad stack and perform substrate package routing
power distribution using Cadence APD (Allegro) or SiP tools
Optimize package pin out incorporating system level trade-offs of pins assignment
Develop methodologies to improve layout environment
and schedule considerations
How You'll Work.
Team & Collaboration
collaborate with Technical Package Lead; cooperation with different design teams; In close co-operation with the SI/PI/HW design teams and product teams
Process & Methodology
Planning, leading projects from start to finish
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