Cerebras Systems

Technology

SeniorFrontEndDesignEngineer(Microarchitecture)

$220–330k ~AI est. Sunnyvale, California, United States
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior Front End Design Engineer (Microarchitecture) at Cerebras Systems. Skills: RTL design, Chip integration, Networking stack. Drive chip design. Develop RTL”

Industry & Context.

Technology
Problems you'll solve

Debug silicon issues

What They're Looking For.

Must Have

Master's degree, 8+ years RTL design, Front End Chip integration, Third-party IP integration, Networking stack experience, TCP/IP experience, RDMA experience, Ethernet experience, PCIe experience, CPU interfaces experience, Serdes technology experience, Python scripting, TCL scripting

Nice to Have

FPGA development toolchain experience, Place and Route experience, Floor planning experience, Timing Analysis experience, Managing external ASIC vendor

What You'll Do.

Work with verification teams

Work with software teams

Work with system teams

How You'll Work.

Team & Collaboration

Design verification teams; Physical design team; Software teams; System teams

Full Job Description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems. Responsibilities Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis. Work closely with PD team members for design closure to meet PPA goals. Work closely with Design verification and DFT teams for achieving the bes

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