SEAKR Engineering
Space Applications
SeniorFPGAEngineer
Neural analysis suggests this role is
optimal for mid candidates.
“Senior FPGA Engineer at SEAKR Engineering. Skills: FPGA design, Verilog, VHDL, RTL debug. Complete FPGA or ASIC design. Develop test bench”
Industry & Context.
Digital lab debug problems
US Citizenship Required
What They're Looking For.
Must Have
10+ years of FPGA experience, FPGA design experience, RTL block completion and review, Code review participation, Significant RTL debug, Working knowledge of CDC, Working knowledge of reset design, Working knowledge of clock design, Solve digital lab debug problems, Use of lab tools
Nice to Have
Knowledge of RTL design techniques for radiation upset mitigation, Experience using multiple RTL languages, Bachelor's degree in Electrical Engineering, Bachelor's degree in Computer Science
What You'll Do.
Complete FPGA or ASIC design
Provide support to junior engineers
Provide technical direction to junior engineers
How You'll Work.
Team & Collaboration
Leading small sized teams
Communication Scope
Written communication; Verbal communication
Process & Methodology
Program schedule expectations
Full Job Description
Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space. Seeking an FPGA Engineer who has extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs. Candidate shall have experience with * Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity * Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs * FPGA technology differences (Xilinx vs Actel/Microsemi) * FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero * Scripting languages such as TCL or Python * Leading small sized teams in order to develop moderately complex systems according to program schedule expectations Required skills * FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design * Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers Knowledge of RTL design techniques for radiation upset mitigation and experience using multiple RTL languages are a plus. ## Qualifications * Candidate shall also have leadership skills and ability to provide support and technical direction to junior engineers. * Clear written and verbal communication skills are required. * A Bachelor's degree in Electrical Engineering or Computer Science is desired. * Must have at least 10+ years of FPGA experience. ## Additional Information Compensation: Base pay range is $130,000-185,000 depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addit
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