Astera Labs
Technology
SeniorFoundryEngineer,SiliconTechnology
Neural analysis suggests this role is
optimal for Senior candidates.
“Senior Foundry Engineer, Silicon Technology at Astera Labs. Skills: Foundry engagement, Silicon technology, Yield improvement, PDK support. Support foundry engagement. Support silicon-to-model correlation”
What You'll Achieve.
Optimize power; Optimize performance; Optimize yield; Reduce tapeout risk
Industry & Context.
Identify risks; Assess product impact; Drive timely resolution; Optimize power; Optimize performance; Optimize yield; Identify process contributors; Investigate yield issues; Investigate process excursions; Troubleshoot failures
What They're Looking For.
Must Have
B.S. or M.S. in EE, Material Science, or related, 5+ years semiconductor device engineering, 5+ years foundry interface experience, 5+ years silicon technology experience, 5+ years process integration experience, 5+ years yield/process correlation experience, Working knowledge semiconductor process flows, Working knowledge device physics, Working knowledge manufacturability, Working knowledge reliability, Working knowledge yield drivers, Experience supporting tapeouts, Experience PDK validation, Experience silicon bring up, Experience analyzing silicon data, Experience analyzing wafer-level data, Experience analyzing process monitors, Experience analyzing product test data, Experience analyzing characterization data, Experience analyzing reliability data, Prior experience at foundry, Prior experience at IDM, Prior experience at fabless semiconductor company, Prior experience at PDK/enablement organization, Familiarity SPICE models, Familiarity process corners, Familiarity device behavior, Familiarity layout effects, Familiarity silicon-to-model correlation, Communicate technical issues clearly
Nice to Have
Advanced FinFET experience, Gate-all-around/nanosheet experience, BiCMOS technologies experience, SRAM design constraints experience, Analog/mixed signal design constraints experience, RF design constraints experience, Serdes design constraints experience, Low power design constraints experience, Benchmarking foundry nodes experience, Using foundry models experience
What You'll Do.
Support foundry engagement
Support silicon-to-model correlation
Support tapeout readiness
Support yield improvement
Analyze process inline data
Analyze silicon test data
Analyze process drift
Analyze process correlation data
Identify process contributors
Investigate yield issues
Investigate process excursions
Perform layout analysis
Support product tapeouts
Support tapeout readiness reviews
Summarize DFM findings
Coordinate waiver disposition
Document process risks
Maintain PDK qualification database
Support technical interactions
Track foundry recommendations
Summarize design impact
Summarize layout impact
Summarize model impact
Summarize signoff impact
Validate model behavior
Compare silicon measurements
How You'll Work.
Team & Collaboration
Internal design teams; CAD layout teams; Product engineering teams; Test teams; Reliability teams; Operations teams; External foundry partners; Physical design teams
Communication Scope
Communicate technical issues
Full Job Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Description We are seeking a Senior Foundry Engineer, Silicon Technology to support foundry engagement, silicon-to-model correlation, tapeout readiness, and yield improvement for advanced semiconductor products. This person will work closely with internal design, CAD layout, product engineering, test, reliability, operations teams and external foundry partners to identify risks, assess product impact, and drive timely resolution of process, PDK, model, DRC/DFM, and silicon-related issues. Responsibilities Include Silicon, process and yield correlation Analyze process inline data, silicon test data, process drift and process correlation data Fine tune processes to optimize power, performance and yield Help identify process related contributors to parametric drift, yield loss, leakage, reliability risk Work with foundry and internal teams to investigate yield issues and process excursions Perform layout analysis where needed to understand process sensitivity, failures Tapeout and DFM support Support product tapeouts, tapeout readiness reviews from a PDK, DRC/DFM, device model and reliability perspective Run or coordinate DFM checks on products and summarize findings for design and layout teams Coordi
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