SeniorEngineer-StandardCellDesign

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Responsibilities** * Design and maintain standard cells for new DRAM products on new technology * Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies * Characterization and modeling of Standard cells to provide timing/power model * Quality Analysis of characterized liberty models in terms of performance, Power and Functionality * Develop automation test bench/flow/tools to improve the work efficiency and help data analysis * Co-work with international colleagues on developing new flows and tools for stdcells design * Ability to identify stdcells design & char pain points suitable for **AI-based automation** and collaborate with cross‑functional teams to deploy scalable solutions. **Requirements** * Good understanding of CMOS circuit design * Good knowledge of CMOS device physics and layout * Experience in total stdcells flow from DTCO development/ spec definition till lib release * RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow * Finefet & planner experience required. * Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. * Experience in Primetime, Solido Analytics * Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision * Experience in Standard Cell design, layout and verification * Experience in Skill, TCL, Perl, Python to do test bench automation and data analysis * Previous work experience in DRAM memory related fields or analog blocks is a plus * Good interpersonal & communication skills and ability to work well in a team * Experience using **AI-assisted tools** to improve stdcells des