Samsung

Semiconductor

SeniorEngineer,PhysicalDesignFloorplan

$124–124k Austin, Texas, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior Engineer, Physical Design Floorplan at Samsung. Skills: Floorplan, Physical Design, EDA flows. Create and optimize top-level floorplans. Drive block-level floor-planning”

What You'll Achieve.

Enable efficient physical-design execution; Ensure robust, high-performance, and low-power implementations; Achieve final GDS delivery; Accelerating adoption of advanced technology nodes; Enabling market-differentiating power, performance, and area (PPA); Silicon reliability; Design turnaround time

Industry & Context.

Semiconductor
Problems you'll solve

problem-solving skills

Eligibility Requirements

Ability to access information subject to U.S. export control restrictions, Eligible to receive a government authorization to access export-controlled information, Not disclose to Samsung any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity

What They're Looking For.

Must Have

5+ years of experience of professional experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 3+ years of experience with a Master’s degree, or 1+ years of experience with a PhD, EDA flows and methodologies, industry standards pertaining to Floor-planning, Top and Block level Floor-planning techniques, partitioning, pinning, budgeting, power-grid implementation, clock distribution, scripting and automation skills in Python, TCL, Shell, or Perl, delivering final GDS for high-performance IPs and SOCs

Nice to Have

sign-off closure flows in deep-submicron technology, physical verification, STA, EMIR, Power

What You'll Do.

Create and optimize top-level floorplans

Drive block-level floor-planning

Execute floor-planning activities

Deliver key floor-planning activities

Drive PPA aspects of floor-planning

Improve floor-planning design methodology

Lead physical-verification convergence

How You'll Work.

Team & Collaboration

Close collaboration with cross-functional design teams; Collaboration with EDA partners; Collaboration with intra-functional groups; Collaborating with Architecture, RTL, PPA, and Physical Design teams; Working across parallel development cycles

Full Job Description

**Position Summary** Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! **Role and Responsibilities** As a Senior Physical Design Floorplan Engineer, you will play a key role in creating and optimizing top‑level floorplans that enable efficient physical‑design execution for SARC/ACL premium IPs. This highly visible position requires close collaboration with cross‑functional design teams, EDA partners, and intra‑functional groups. You will contribute strong problem‑solving skills and a deep understanding of floor‑planning challenges and best‑practice methodologies, ensuring robust, high‑performance, and low‑power implementations across Samsung’s premium mobile device tiers. Key responsibilities include: * You are a key contributor for the top‑level floorplan, driving block‑level floor‑planning and execution * You execute and deliver key floor‑planning activities (placement, shaping, pinning, methodology) with production‑grade quality * You drive the critical PPA aspects of floor‑planning by collaborating with the Architecture, RTL, PPA, and Physical Design teams * You work with the CAD team to continuously improve the floor‑planning design methodology * You lead the physical‑verification convergence of the top‑level floorplan to achieve final GDS delivery **Skills and Qualifications** * 5+ years of experience of professional experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 3+ years of experience with a Master’s degree, or 1+ years of experience with a PhD * Skille

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