Analog Devices
Semiconductor
SeniorEngineer,PhysicalDesignEngineering
Neural analysis suggests this role is
optimal for Senior candidates.
“Senior Engineer, Physical Design Engineering at Analog Devices. Skills: Physical Design Engineering, Mixed Signal SoCs, PnR Signoff. Innovate on the flows to meet QoR targets. Ensure predictability”
Industry & Context.
Meet QoR targets
10% of the time
What They're Looking For.
Must Have
BTech/MTech degree in Electrical/Electronic, 4-8 years of experience in Digital place and route, Hands on experience with implementation (PnR Signoff), Hands on experience in handling tapeout, Proficient in TCL, Proficient in Perl
Nice to Have
Good understanding on device/interconnect and circuit aspect of UDSM technologies
What You'll Do.
Innovate on the flows to meet QoR targets
Ensure predictability
Full Job Description
**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). **Senior/Lead PD Engineer** ADI is looking for Senior/Lead PD Engineer for the development of complex mixed Signal SoCs. These chips are manufactured in most leading edge process nodes and high speed clock rates. These SoCs involve multiple processor cores and speed signal processing hardware running at high speed. **_Position Requirements_** * BTech/MTech degree in Electrical/Electronic from a reputed institute with 4-8 years of experience in the field of Digital place and route * Hands on experience with the implementation (PnR Signoff) of complex high speed SoC designs in cutting edge process technologies (22 nm, 16 nm, 7 nm, etc). * Hands on experience in handling the tapeout of complex high speed SoC designs in cutting edge process technologies * Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction * Strong expertise in Static Timing analysis , constraint development and sign off. * Innovate on the flows to meet the QoR targets and ensure predictability * Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage. * Being proficient in TCL, Perl etc. _For positions requiring access to technical data, Analog D
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