Micron Technology

Technology

SeniorEngineer-MemoryCellTestStructureDesignandLayout

$950–1500k ~AI est. Jalisco, Mexico FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior Engineer - Memory Cell Test Structure Design and Layout at Micron Technology. Skills: Layout, Validation, EDA Tools. Support process development activities. Engage with Process Integration”

What You'll Achieve.

Ensure accurate parametric correlation; Ensure accurate debug; Contribute to standardized test structures; Contribute to novel test structures

Industry & Context.

Technology
Problems you'll solve

Problem-solving skills; Debug

What They're Looking For.

Must Have

5 years of experience, Proficiency in EDA tools, Cadence Virtuoso Layout, Schematic Editor, Calibre proficiency, Excellent circuit design skills, Excellent layout skills, Excellent schematic skills, Excellent verification skills, DRC, LVS, Circuit simulation (hspice), Excellent knowledge of semiconductor device physics, Excellent knowledge of device operation, Excellent knowledge of parametric testing, Excellent knowledge of DFM, Good knowledge of DRAM, Good knowledge of NAND Memory Array, Good knowledge of design architectures, Good knowledge of Fab processes, Good knowledge of failure modes, Excellent problem-solving skills, Excellent communication skills, Global outlook, Sense of ownership

Nice to Have

Master of Science in Electrical or Microelectronic Engineering, 3 years of experience, Proficiency in Perl, Proficiency in Skill code, Proficiency in UNIX shell scripting, Willingness to learn new skills, Explore unfamiliar concepts

What You'll Do.

Support process development activities

Engage with Process Integration

Engage with Product and Die Design

Engage with Electrical Characterization

Engage with Advanced Mask Development

Engage with Design Rule teams

Interpret electrical DUT definition

Implement novel solutions

Study failure mechanisms

Monitor health of silicon

Assist with parametric correlation

Verify test structure documentation

Validate test structure documentation

Verify related parametric information

Validate related parametric information

How You'll Work.

Team & Collaboration

Cross-functional teams; Process Integration; Product and Die Design; Electrical Characterization; Advanced Mask Development; Design Rule teams

Communication Scope

Communication skills

Full Job Description

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, our vision is to transform how the world uses information to enrich life for all. We are a global leader in memory and storage solutions. We accelerate the transformation of information into intelligence. We encourage the world to learn, communicate, and advance faster than ever. In the Research and Development (R&D) Scribe Design Group, we drive innovation in advanced technology development through scribe test structure design, layout, and validation. Our team collaborates across multiple disciplines to enable cutting-edge semiconductor solutions. As a Scribe Array Design Engineer, you will design and validate memory cell & support circuitry-based test structures, manage design revisions, and partner with cross-functional teams to support process development and manufacturing integration. You will play a critical role in ensuring accurate parametric correlation and debugging, while contributing to the creation of standardized and novel test structures. **Responsibilities:** * Support process development activities through memory cell-based test structure solutions by actively engaging with Process Integration, Product and Die Design, Electrical Characterization, Advanced Mask Development and Design Rule teams. * Interpret electrical DUT (Device under Test) definition and build completed TEGs (Test Element Groups) with high confidence functionality on Silicon. * Implement novel solutions as the need arises to study the failure mechanisms and to monitor the health of silicon. * Assist with parametric correlation and debug to ensure design accuracy. * Verify and validate test structure documentation and related parametric information. **Minimu

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