Micron Technology
Technology
SeniorEngineer-DEGLayout
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optimal for Senior candidates.
“Senior Engineer- DEG Layout at Micron Technology. Skills: Layout design, Layout verification, Analog layout, Custom digital block. Responsible for layout design and development. Perform layout verification”
What You'll Achieve.
On-time delivery of block-level layouts; Meet project schedule/achievements
Industry & Context.
Problem-solving skills
What They're Looking For.
Must Have
5 to 8-year experience in analog/custom layout design, Expertise in Cadence VLE/VXL, Expertise in Mentor Graphic Calibre DRC/LVS, Hands on experience in creating layout of critical blocks, Good understanding of Analog Layout fundamentals, Understanding layout effects on circuit, Ability to understand design constraints, Excellent command and problem-solving skills in physical verification
Nice to Have
Multiple Tape out support experience
What You'll Do.
Responsible for layout design and development
Perform layout verification
Responsible for development of digital block layouts
Responsible for basic understanding of skill coding
Responsible for on-time delivery of block-level layouts
Demonstrate leadership skill in planning
Demonstrate leadership skill in area/time estimation
Demonstrate leadership skill in scheduling
Demonstrate leadership skill in delegation
Demonstrate leadership skill in execution
Guide developing team members
Review team members work
Contribute to effective project-management
Effectively communicating with Global engineering teams
Responsible for reducing layout effort using AI tools
How You'll Work.
Team & Collaboration
Global engineering teams
Communication Scope
Verbal communication; Written communication
Process & Methodology
Planning, Estimation, Scheduling, Delegation, Execution, Project management
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. _Role and Responsibilities_ * Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. * Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation. * Responsible for development of digital block layouts using auto placement and route tools * Responsible for basic understanding of skill coding and automation * Responsible for on-time delivery of block-level layouts with acceptable quality. * Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. * Guide developing team members in their execution of Sub block-level layouts & review their work * Contribute to effective project-management. * Effectively communicating with Global engineering teams to assure the success of layout project. * Responsible for the reducing the layout effort by using AI tools _Qualification/Requirements_ * 5 to 8-year experience in analog/custom layout design in advanced CMOS process. * Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. * Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., * Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) * Understanding layout effects on the circuit such as speed, capacitance, power and ar
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