SeniorDVEngineer

## Description Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work. ## Requirements HDL & Verification Methodology · Proficiency in Verilog and SystemVerilog · Working knowledge of UVM architecture and methodology · Ability to write verification tests within an existing environment Programming & Scripting · Some experience scripting in Perl, Python, or bash ## What you bring to this role 4+ years of design verification experience in the semiconductor industry ## Additional Information This is a full time, exempt position, based out of our Saratoga office.  The target base pay for this position is $120,000 - $220,000 annually.  The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience.    We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed.   E-Space is not currently abl